Design Article
Hi def video scaler ASIC development from FPGA
Wolfgang Hoeflich, Senior Field Applications Engineer, AMI Semiconductor
9/29/2006 3:40 AM EDT
This article details the implementation and verification flows of a high-definition video scaler ASIC implemented in a 0.18um standard cell technology. The Anchor Bay Technology application targets the consumer market space for high-definition video sources (for example, HD-DVD and Blu-ray players). Achieving quick time-to-market was critical for the success of the project, in addition to beating competitive products in cost, features and ease-of-use. An FPGA prototype was used for at-speed verification of all functionality, especially image quality enhancements.
Figure 1: Test set-up used for evaluation and debugging FPGA and ASIC design.
The job of a video scaler is to reformat the incoming image to get the most out of the panel's viewing area without causing distortions of the image; in particular areas that have a high level of detail. The effects of a high-quality scaler are easily observed on a high-resolution display with a viewing area above 32 inches, for example, when a standard interlaced TV source is adapted to a progressively scanned HD LCD or plasma panel with a different aspect ratio.
A video scaler is able to produce a converted image in a wide range of resolutions and refresh rates (frame rate conversion), completely independent of the video format, interlaced and non-interlaced, while exactly matching the native resolution of the display.
Figure 2: Scaler system diagram
Figure 2 illustrates the possible input sources and output configurations supported by the Anchor Bay Technology (ABT) 1010/18 video scaler. The optional SDRAM interface allows full frame rate conversion support. The video scaler can accept a high-definition video source such as 720p and process it using sophisticated algorithms to change image resolution, refresh rate and aspect ratio to exactly match the desired output specifications of the display.
Next: The scaler engine
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