A "How To" tutorial on logic analyzer basics for digital design

In order to implement transitional timing, a "transition detector" could be used at the input of the timing analyzer along with a counter. The timing analyzer will now store only those samples that are preceded by a transition, together with the elapsed time from the last transition. This approach permits using only two memory locations per transition and no memory at all if there is no activity at the input.

In our example, the second, third, fourth and fifth bursts can be captured, depending on how many pulses per burst are present. At the same time, we can keep the timing resolution as high as 4 ns (Fig 3).

2. Sampling at high resolution.
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3. Sampling with a transition detector.
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Glitch capture: Glitches have a nasty habit of showing up at the most inopportune times with the most disastrous results. Consider an example where a system crashes periodically because a glitch appears on one of the lines. One alternative is to use an analyzer without glitch trigger capability, sit in front of the machine, press the run button, and wait until the glitch appears. Since this condition occurs infrequently, storing data all the time (assuming there is enough storage capability) would result in an incredible amount of information to sort through.

Now consider a timing analyzer that samples the incoming data and keeps track of any transitions that occur between samples, so it can readily recognize a glitch (in this context, a glitch is defined as any transition that crosses logic threshold more than once between samples). To recognize a glitch, the analyzer is "taught" to keep track of all such multiple transitions and display them as glitches.

While displaying glitches is a useful capability, it can also be helpful to have the ability to trigger on a glitch and display data that occurred before it. This can help determine what caused the glitch. This capability also enables the analyzer to capture data only when it is required – when the glitch occurs.

Triggering the timing analyzer: A logic analyzer continuously captures data and stops the acquisition after the trace point is found. Thus a logic analyzer can show information prior to the trace point, which is known as negative time, as well as information after the trace point.

• Pattern trigger
  Setting trace specifications on a timing analyzer is a bit different from setting trigger level and slope on an oscilloscope. Many analyzers trigger on a pattern of highs and lows across input lines.

  To make things easier for some users, the trigger point on most analyzers can be set in binary (1's and 0's) hex, octal, ASCII, or decimal numbering. Using hex for the trigger point is particularly helpful when looking at buses that are 4, 8, 16, 24, or 32 bits wide. Imagine how cumbersome it would be to set a specification for a 24-bit bus in binary. 
   

• Edge trigger
  When the trigger level knob on a scope is adjusted, think of it as setting the level of a voltage comparator that tells the scope to trigger when the input voltage crosses that level. A timing analyzer works essentially the same on edge triggering except the trigger level is preset to logic threshold.

  While many logic devices are level-dependent, clock and control signals of these devices are often edge-sensitive. Edge triggering allows users to start capturing data as the device is clocked.

  The analyzer can capture data when the clock edge occurs (rising or falling) and catch all of the outputs of the shift register. In this case, the trace point would have to be delayed to take care of the propagation delay through the shift register.

State analyzer basics
If an engineer has never used a state analyzer, one may think it's an incredibly complex instrument that would take a large time to master. The truth is many hardware designers find a state analyzer to be a very valuable tool.

When to use a state analyzer: A "state" for a logic circuit is a sample of a bus or line when its data is valid. Consider a simple "D" flip-flop. Data at the "D" input will not be valid until a positive-going clock edge comes along. Thus, a state for the flip-flop is when the positive clock edge occurs.

Imagine there are eight of these flip-flops in parallel and all of them are connected to the same clock signal. When a positive transition occurs on the clock line, all eight will capture data at their "D" inputs. Again, a state occurs each time there is a positive transition on the clock line. These eight lines are analogous to a microprocessor bus. If a state analyzer is connected to these eight lines and told to collect data when there is a positive transition on the clock line, the analyzer would do just that. Any activity on the inputs will not be captured by the state analyzer unless the clock is going high.