Consider the general clocking scheme for an MCU where the input
clock frequency is 32,768 Hz and – in the timer module – this clock frequency is divided by 64. Thus, subsequent timer interrupts occur at every 1/512th of a second.
Applying the above equations: f * N = 512.
If the required number of PWM levels available in the system (N) is 4, then the frequency of the output PWM signal will be 512/4 = 128 Hertz. The system designer should take care of the fact that the generated PWM frequency does not create flicker on the LCD or other undesirable effects.
In a particular user scenario, let's assume that the user wishes to select an LCD brightness level (k) of say, 3. Then, the algorithm would generate waveforms as illustrated in Fig 5.
5. Example timing diagram for PWM level (k=3).
(Click this image to view a larger, more detailed version)
Advantages: This algorithm enables an MCU with a single timer to provide the functionality of RTC and PWM, although at the cost of additional MIPS. Single timer-based MCUs are generally cheaper than their multi-timer counterparts, so this algorithm can help in reducing the bill-of-materials (BOM) of cost-sensitive systems.
Limitations: There is a trade-off between the number of PWM levels supported (N) and the PWM frequency (f). If the number of the PWM levels (N) is required to be more, the PWM frequency needs to be lower (and vice versa) so as to ensure that the interrupt frequency is maintained. A lower PWM frequency (f) implies increased chances of visible flicker on the display. A low-pass filter can be inserted in the electrical circuit with a very low cutoff frequency, but this would impact the design in two ways:
- The time constant is now increased, which means that it would require added time for the effect of user-initiated brightness changes to be perceived on the display.
- Higher and more bulky values of capacitance are required to attain lower cutoff frequencies.
Hence the PWM frequency must be intelligently chosen so as to avoid the need for
additional hardware filters.
Another consideration is that the method described here uses minimal hardware resources (a single timer) at the cost of more computational CPU cycles to generate the RTC and PWM outputs.
The algorithm described in this paper can be implemented on any MCU and has been tested on the MSP430F2xx family of devices. The following is a summary of the footprint required for this algorithm on the MSP430:
- Flash footprint (program memory): 20 bytes for a basic implementation.
- RAM footprint (data memory): 6 bytes for temporary storage (excluding RTC
- MIPS footprint: The program control enters WDT routine for every 1/ (F * N)
seconds. Execution time for updating PWM routine is 40 cycles and RTC routine
is about 60 cycles. Hence the average MIPS (averaged over one second) would
be: Avg. MIPS = (40 x 511 + 60) = 0.0205 MIPS.
The CPU can be put in an appropriate low power mode for most of the time, thereby saving battery life, which is critical for many portable systems.
Ajit Basarur is an Engineer in the Multimedia Systems Group of Ittiam Systems in Bangalore, India. Ajit – who was authored the IEEE paper Power Management in Portable Media Players may be contacted at email@example.com.
Shantanu Prasad Prabhudesai is an Engineer in the Multimedia Systems Group of Ittiam Systems in Bangalore, India. Shantanu – whose college degree are M.Tech, CEDT (IISc), Bangalore, India – may be contacted at firstname.lastname@example.org.
Ritesh Ramesh Parekh is a Lead Engineer in the Multimedia Systems Group of Ittiam Systems in Bangalore, India. Ritesh – whose college degree are M.Tech, CEDT (IISc), Bangalore, India – may be contacted at email@example.com.