New FPGA meets handheld price, power, and space requirements

1. NVCM enables lowest price, power, and space in new FPGA technology.

2. Classic SRAM FPGAs are configured from external sources on power-up.

Two chips cost more than one chip, they consume more power, and they occupy more space. Thus, the foundation technology that enables the lowest price, power and space associated with SiliconBlue's ground-up FPGA design is Non-Volatile Configuration Memory (NVCM) on a 65 nm low power CMOS process. Using a standard process from TSMC, the NVCM is embedded into an SRAM FPGA (Fig 3).

3. SiliconBlue SRAM FPGAs are configured from on-chip, embedded NVCM, saving cost, power and space.

As the embedded NVCM area is less than 3% of the total chip area, the total cost of the single chip solution, is much lower than the two-chip solution. Compared to non-volatile PLDs on older 130 nm and 180 nm flash processes, SiliconBlue's 65 nm NVCM provides the lowest cost-per-unit-logic and will continue to lead as the NVCM is scalable to 40 nm and beyond.

Low-power process
SRAM FPGAs have dominated programmable logic due to the low cost afforded by leading-edge, high-performance process nodes. Now, SiliconBlue is applying this leading-edge strategy to handheld FPGAs by utilizing TSMC's 65nm LP (low-power) process node. Previous leading process nodes were high-performance and high-power, and therefore were not suitable for handheld requirements. Beginning at 65 nm, however, the trend has switched to low-power as the first available on a new process node.

Advantages of the leading process node are, of course, smaller transistors, providing higher logic capacity and lower capacitance at a lower core voltage, resulting in lower active power, proportional to CV². Higher logic capacity translates into lower cost per unit logic than older process nodes.

Power modes defined by handset designer
SiliconBlue uses the same definitions for power modes as handset designers. First, the Operating Mode refers to normal operation in the MHz range where the handheld device is performing a specific operation. Second, the Stand-by Mode is the power saving mode operating in the kHz range, where the handheld device is waiting for the next operation to be called. Typically, in Stand-by mode, operation is at 32 kHz supplied by the real time clock. These handheld modes are detailed in Table 1.

Table 1. Definition and comparison of power modes.

SiliconBlue specifies power for Operation as Active Fast Power (AFP). At 32 MHz, the iCE65L04 device consumes 9 mW compared to competing SRAM FPGAs devices at 60 to 62 mW and other PLDs at 30 to 170 mW. Clearly, competing SRAM FPGAs consume too much power to be used in handheld devices. For example, a 60 mW FPGA with 1.2V core would consume the entire capacity of a 1000 mA hour battery in less than 20 hours.

SiliconBlue specifies power for Stand-by as Active Slow Power (ASP). At 32 kHz, the iCE65L04 device consumes 0.025 mW compared to competing SRAM FPGAs devices at 30 to 36 mW and other PLDs at 0.044 to 0.350 mW. Again, at 30 to 36 mW, competing SRAM FPGAs consume too much power to be used in handheld devices. Compared to other PLDs, the iCE65L04 device consumes significantly less Stand-by power.

Other PLD suppliers specify Static modes of operation with the clock stopped at 0 MHz. In the real world, these modes are rarely used by handset designers as they require additional hardware and software resources to stop the clock. The preferred method of Stand-by is to keep the heartbeat alive at 32 kHz, awaiting the next operation such as detecting a keypad click.

Other PLD suppliers also specify Power Down modes such as sleep, hibernate, and freeze, where state is maintained while functionality is disabled. Once again, these modes are rarely used by handset designers as they require additional hardware and software resources. Furthermore, there is a paradox here. PLDs are often used in control and power management. How can the PLD wake itself up when its functionality is disabled? Additionally, these modes require recovery time to wake up, further complicating design.