Altera Stratix IV User Guide Lite

What is the purpose of this paper?
This paper provides potential users an easily read and easy-to-understand overview of the capabilities of the device functions of Altera's Stratix IV FPGAs. It succinctly describes the feature set, the architecture innovations, and the process techniques that when combined make the Stratix IV FPGA the industry leader in both power and performance. Further, the article describes the functionality of these devices in far more detail than in the data sheet, but avoids the minute implementation details covered in the Stratix IV FPGA Device Handbook.

Designers contemplating designing with Stratix IV FPGAs may face a hurdle or two. The data sheet provides a very condensed overview of the complete device family, but does not describe the capabilities in enough detail. By comparison, the Device Handbook provides all the details that the designer needs, but — at 1,200+ pages — it probably will require several weeks of work to read and understand all of the details.

This paper describes the capabilities (what you can do) in detail, but leaves out the implementation details (how to utilize the capabilities). The idea is to give the designer enough information to evaluate the capabilities, without requiring weeks of study. Altera believes that system architects and designers who are in the early stages of FPGA device planning and evaluation will find the information presented here to be a valuable source of information before beginning a Stratix IV design.

Stratix IV Product Overview

Gigabit Transceivers
Stratix IV GT devices provide up to 24 transceivers supporting 9.95 to 11.3 Gbps, with a Physical Coding Sub-layer (PCS). Up to 8 additional transceivers are available supporting 2.5 to 8.5 Gbps, with PCS. Additionally, up to 16 additional transceivers are available supporting 2.5 to 6.5 Gbps, without PCS. The Stratix IV GT transceivers eliminate the need for an external 10G PHY device and thus enable the preferred implementation of 802.3ba (40G/100G) recommended configuration.

Stratix IV GX devices provide up to 32 full-duplex CDR-based transceivers with PCS, PMA and PCI Express Hard IP blocks (Figure 1). These transceivers support serial data rates between 600 Mbps and 8.5 Gbps. Additionally, up to 16 full-duplex CDR-based transceivers, supporting serial data rates between 600 Mbps and 6.5 Gbps are provided.

Click on image to enlarge.

Figure 1. Stratix IV GX Transceiver Block Diagram

Stratix IV transceivers support the stringent jitter requirements of protocols such as PCI Express Gen II and CEI-6G for Interlaken implementation. In addition they support PCI Express Gen 1; XAUI (3.125 Gbps to 3.75 Gbps for HiGig support); GIGE (1.25Gbps); Serial RapidIO' (up to 3.125 Gbps); SONET/SDH up to OC-96 and both HD and 3G Serial Digital Interface. The transceiver channels also support basic single-width (600 Mbps to 3.75 Gbps) and basic double-width (1 Gbps to 8.5 Gbps) flexible functional modes to implement proprietary protocols.

The Stratix IV GX transceivers are structured into full-duplex (Transmitter and Receiver) six-channel groups called transceiver blocks that vary in count from device to device. Channels can be dynamically reprogrammed to support multiple protocols and data rates without disturbing the operation of any other part of the FPGA. Each transceiver has dynamically programmable differential output voltage (VOD) and pre-emphasis settings for improved signal integrity. To compensate for frequency-dependent losses in the physical medium, each transceiver supports adaptive 4-stage receiver equalization with up to 17dB of gain. In addition, selectable on-chip termination resistors help improve signal integrity on a variety of transmission media.

The programmable transceiver-to-FPGA interface supports data transfers in a wide variety of widths from 8 to 40 bits. Receiver rate-matching FIFO buffers resynchronize the received data with the local reference clock while phase compensation FIFO buffers perform clock domain translation between the transceiver block and the logic array.