Less is More for DAC 2004

Looking for the common threads within this year's Design Automation Conference (DAC), one can point to the usual suspects. These include continued industry consolidation, the drive to smaller process geometries, an increased emphasis on high-level system design and design for manufacturability (DFM), and the increasing attention designers are paying to silicon IP as a product differentiator. In addition, this year's show and conference also brought out an additional design parameter of increasing concern—power dissipation—as chips migrate to 90nm and beyond. The following summarizes some of the most important topics covered at DAC 2004, centered, more or less, on a "less is more" theme.

Mentor to Buy 0-In
This acquisition seems to make a lot of sense. 0-In's assertion-based functional-verification products are a good complement to Mentor's existing chip-verification tools, which are strong in the areas of emulation, simulation, and hardware/software co-verification. In the eight years of its existence, 0-In has not gained widespread recognition for and use of its verification software, due in part to its tools not being part of a more complete verification suite. Inclusion of the 0-In tools in Mentor's integrated tool suites will help remedy this situation.

Hier Design Acquired by Xilinx
This is another good deal for both companies. Relative newcomer Hier Design, with Xilinx as one of its initial investors, develops hierarchical floorplanning and analysis software (the PlanAhead floorplanner) for designing high-performance FPGAs. Xilinx recognizes the need to make high-end FPGA design more "ASIC-like," including the use of floorplanning tools to allow closer convergence of logical and physical design. This is particularly important with the recent introduction of Xilinx's Virtex-4 platform FPGA family that uses the company's domain-specific Advanced Silicon Modular Block (ASMBL) architecture. The PlanAhead tool already works with Xilinx's ISE design suite, so the Hier Design acquisition strengthens the Xilinx FPGA design methodology and keeps the Hier Design technology out of competitors' hands.

MatrixOne to Buy Synchronicity
This acquisition also works for both parties, but for different reasons. Synchronicity, a developer of design reuse, design collaboration and design-management software for IP-based SoCs, has pretty much been stagnant over the past few years and needed a boost. MatrixOne helps companies collaboratively develop, build, and manage products through a combination of product lifecycle management (PLM) products and services. Synchronicity's technology lets MatrixOne add chip- and silicon-IP design reuse and collaboration software to their system-level expertise. MatrixOne also picks up over 100 new customers—all for the bargain basement price of $15M.

VSIA Reorganizes
The VSI Alliance (VSIA), comprising system houses, semiconductor vendors, EDA companies and IP providers, has the mission of developing solutions to help vendors and customers more efficiently adopt and use SIP. However, with its myriad Development Working Groups (DWGs), Technical Committee (TC), and Adoption Groups (AGs), VSIA was itself not very efficient in getting its work adopted by the electronics industry. To overcome this problem, and fitting in a "less is more" DAC theme, VSIA has "slimmed down." The Alliance has replaced DWGs, AGs, and the TC with three Pillars—IP Quality, IP Protection, and R&D. Each pillar has at least four large VSIA member companies to help assure industry adoption of work developed by that Pillar. VSIA can spawn additional Pillars from the R&D Pillar to cover topics such as analog, signal integrity, implementation verification, and platform-based design. The "'lighter" VSIA should prove more efficient in implementing ideas within the chip-design community, but only if the organization attracts and keeps good members, and develops new Pillars as industry needs develop.

SPIRIT Announces First Specification
The Structure for Packaging, Integrating, and Re-using IP with Tool-flows (SPIRIT) Consortium, launched at DAC last year, used DAC 2004 as the venue for announcing SPIRIT 1.0 for member review. SPIRIT 1.0 covers RT-level SoC design encapsulation for automated IP integration along with interoperability of configurable and non-configurable IP with multiple tool sets. The intent of the standard is to allow SPIRIT-compliant IP to be used in design tools that support the SPIRIT format, including tools for system design, co-verification, simulation, and synthesis. SPIRIT has also grown and now has over 20 members, with ARM, Cadence, Mentor, Philips, ST Micro, and Synopsys as the consortium's founding members.

Reference Design Flow Addresses Power Closure
In early June, TSMC announced the newest version of their reference design flow linking process technology and EDA design tools, Reference Flow 5.0. The new reference flow builds upon its predecessor with power-consumption and power-integrity capabilities, along with including point tools from Apache (power integrity), Atrenta (netlist screening), and Optimal (integrated chip and package design) within Cadence and Synopsys design flows (Figure 1). Among the power-closure features provided or supported by Reference Flow 5.0 are dynamic-power optimization (sleep-mode power shutdown and standby-mode voltage scaling), leakage-power optimization (multi-VT libraries, power shutdown, and voltage scaling), and integrated chip and package IR-drop analysis. Designers can use the reference flow for TSMC's 130nm and 90nm CMOS technologies.

Figure 1:  Comprising point tools in a mainstream chip-design flow, TSMC's design reference flow helps you achieve power closure by addressing power consumption and power integrity. This figure show the reference flow (left) applied to a Synopsys design flow; a similar reference flow applies to Cadence's design tools.

New Features Enhance Power-Design Tools
A leading provider of power-analysis and -optimization tools, Sequence described three power-closure announcements at DAC. A new release of the company's CoolTime dynamic-power analysis tool features a 4X-speed improvement with a 3X reduction in memory footprint. The new version allows designers to do a voltage-drop analysis on a 20-25M gate design overnight. Sequence's Power Theatre-nm, for large SoC power analysis, includes clock-gating power analysis at the RT-level, helping designers understand how downstream tools can use and, if necessary, enhance integrated clock cells to optimize power. The tool now also supports 64-bit Linux for improved design capacity. Finally, Sequence's newest PhysicalStudio with physical power optimization has leakage-power optimization for multi-VT libraries to help reduce dynamic and leakage power. The tool handles multiple (more than two) threshold levels while also maintaining electrical integrity to minimize design-closure iterations (Figure 2).

Figure 2:  PhysicalStudio lets designers simultaneously optimize for several design parameters—power, voltage drop, timing, and signal integrity—by using cell resizing and multi-VT cell swapping to trade off timing slack for power reduction.

SystemVerilog Tools
Developed by industry standards organization Accellera, SystemVerilog is a major extension of Verilog for improving design productivity of large gate-count, IP-based, bus-intensive chips. Operating at a higher abstraction level than Verilog, SystemVerilog primarily addresses the chip implementation and verification flow, with links to the system-level design flow. Bluespec has developed a SystemVerilog-based tool suite that uses SystemVerilog's verification assertions in the design space. This lets designers work at different levels, from transaction to implementation-target hardware. The Bluespec synthesis and compiler (assertion scheduler) tools, operating at the front end of current chip-design flows, generate both Verilog for synthesis and simulation tools, and cycle-accurate C code for accelerated simulation (Figure 3).

Figure 3:  Bluespec's SystemVerilog tools let the designer work at a level above RTL, accelerating design time. The tools output synthesizable Verilog and cycle-accurate C for faster simulation.

Full System Simulation
Virtutech recently released Version 2.0 of Simics, the company's full-system, "real world" simulation platform. Simics 2.0 creates a controlled and deterministic virtual test environment to simulate both single processor and multiprocessor systems. The environment provides a common infrastructure for several tasks, including microprocessor design; memory hierarchy design; component development and testing; automated software quality testing; SoC virtual prototypes; hardware/software co-simulation; and firmware, driver, and operating-system development. Running at speeds over one billion simulated instructions per second, the software can simulate heterogeneous systems with several different processor architectures, even sharing memory between them. Simics also offers distributed simulation capability, which can support several simulation processes on one or more machines sharing the same virtual time. The simulation platform currently supports simulation models for instruction-set architectures for Alpha, ARM, IA-64, MIPS, PowerPC, SPARC V9, x86, and AMD64 processors.

Jim Lipman is currently the President and Editor-in-Chief of SemiView Inc., a new company providing business, financial, and technology analysis, research, and editorial information for the rapidly growing Application-Adaptable Integrated-Circuit (AAIC) industry. His job experience includes chip-design R&D, marketing, marcom, technical editing, and on-line publishing of technical content for engineers.