System-on-Chip (SoC) device and reconfigurable platform-based silicon solutions combine embedded hardware and software with a staggeringly high level of complexity. While hardware and software development processes can exist in isolation, bringing them together to create devices that will work as expected and hit their market on time, is proving to be an increasingly difficult challenge.

The dilemma facing design teams is only growing, due in large part to inconsistencies of data described within hardware and software specifications. This is now being addressed through the adoption of non-intrusive software and methodologies that complement existing intellectual property (IP) and SoC design flows. By focusing on the need for effective data flow management, it is possible to ensure that data interfaces described within all product specifications are consistent and remain so throughout a project development cycle.

This methodology includes two critical steps for a successful data flow. The first is the need to capture, validate and maintain data in a central location that describes interfaces within a system at the IP and SoC level. The second step is to derive output views from the data required by various designers engaged on a development project. These views consist of product specification documents and actual design code that all refer to, or operate on, this common data.

The first step ensures that there is only one master description for the system and its IP blocks and interconnect fabric. Typical objects include bus interface registers, their constituent bitfields and enumerations for IP blocks, the on-chip system bus and its transactors, either masters or slaves. This allows data to be checked for inconsistencies—duplicate names or overlapping address spaces—at the source. When changes are necessary, it means that they are made in just one place, ensuring that product documentation and design files remain synchronized.

The second step, which automates the creation of these views, avoids error-prone manual tasks. Hand written and manually interpreted specifications typically result in inconsistencies because hand-written code is often poorly documented.

Figure 1:  A two step methodology for improving data flow management involves capturing, validating and maintaining data in a central location that describes interfaces within a system at the IP and SoC level. The second step is to derive output views from the data required by various designers engaged on a development project.

Automation produces maintainable views, easing final system integration with a quality process to effectively manage the increasing complexity of data flows. Providing designers with automated software to package and deploy IP in a repeatable and reliable manner offers savings in development costs and increased productivity. This process facilitates the concurrent development and test of hardware and software, as well as the early generation of systems documentation.

The SoC device and platform-based silicon solution is a complex embedded electronic device that comprises one or more processors and associated peripheral IP blocks, including memory, all of which are connected via an addressable bus.

Each peripheral block interfaces to the system bus through a series of registers made up of bit-fields of various sizes, typically with a variety of access mechanisms. In the most complex systems, these bit-fields may overlap and have different meanings dependent on the access mechanism used.

As design teams push toward more integrated devices, transistor densities have doubled every 12-18 months, as predicted by Moore's Law. This has been compounded by new architectures introduced on three-year cycles.

Managing IP block complexity and system descriptions through a manual process is time consuming and error prone because design teams usually involve many groups—hardware designers, in-house or external IP developers, software developers, verification teams and systems integrators. Each group needs the same data, but they need it to be presented in different forms. Also, it is not uncommon for change to occur during the development process. Changes impact all aspects of the development process and need to be reliably communicated to the various members of a project team. Experience shows that there are far too many opportunities for things to go wrong, either as a result of misinterpretation or through the lack of formalized communication.

Worse yet, specification data is rarely kept in one place or it only exists as a static written document and is left to each development group to interpret. The result is design mismatches and errors that, at best, cause project delays but more often than not lead to extremely costly respins of silicon. With the cost of 90nm mask sets approaching $1 million, it is not hard to see how unnecessary development costs can mount.

Silicon respins resulting in development overruns are one of the biggest factors in being late to market. Recent research by Collett International revealed that 52% of complex application specific integrated circuits (ASICs) required a respin and the reason was largely due to functional errors. Implementation errors were the most common cause of these functional problems with changes in the specification following a close second.

More than 50% of all ASIC design starts are now SoC devices and the figure is still growing. As a consequence, more design teams are challenged to devise a strategy for hardware/software co-design and development. With integration in silicon sometimes incorporating several complex processing cores, hardware and software development within SoC design must be closely coupled. It needs to be performed in parallel to meet critical time to market delivery of a total end system.

Compounding these technology challenges is the continual market pressure to produce next-generation products more quickly. Companies face ever shortening windows of opportunity—shorter periods in which they must recoup their development costs and make a profitable business. With a methodology that allows development costs to be amortized over many projects, huge savings in development costs and effort can be achieved.

The implementation of an effective design flow is a critical part of any development process. Often, this involves dedicating centralized resources to create environments for hardware and software development, producing a contiguous software flow that allows designs to move smoothly from one stage to another. And yet, despite its critical importance to embedded design—SoC and re-configurable platform development—little consideration is given to the flow of product specification data within these design flows.

While hardware and software design flows tend to be relatively self-contained, data flow diverges at the top of the chain, it must remain consistent whatever its destination. Equally, it needs to flow smoothly from one design stage to another. Additionally, the more efficient the design flow, the more obvious the need becomes for better data flow management software. Without the effective flow of data, even the best design flow is vulnerable to the potential that exists for the introduction of errors in the development process.

Through the use of a centralized database for saving IP block and system data, design teams can separate interface definitions from target environments. For example, a designer can specify registers for an IP block without having to consider the bus where registers must connect or where they will need to be placed in the overall processor memory map. This approach allows IP blocks to be ported from one system to another, and swapped between different system architectures.

The split between hardware and software functionality flows from the definition of the system architecture that follows from a full analysis of the product requirements and specifications. As design complexity consumes a project cycle, the need is great for a methodology that provides effective data flow management between both disciplines.