In my pre-Design Automation Conference (DAC) article, I discussed a number of important products in several key areas that vendors would be showing in New Orleans. With the conference concluded, here are a few more products and announcements of special interest.

DSP Design
Two keys to any successful new design tool or methodology are improved productivity or results, and ease of use. AccelChip appears to have this recipe with an upcoming EDA tool for designers who need to implement DSP algorithms into FPGAs. The company's AccelFPGA will let DSP designers develop their DSP algorithms in The MathWorks' familiar Matlab environment and then synthesize the algorithms directly to a targeted FPGA architecture. The tool, which also has links to The MathWorks' Simulink system-level DSP design tool, creates an RTL model of the hardware-based algorithm implementation, along with a simulation testbench, optimized for the user's specific FPGA architecture—no need to manually develop functional specifications or simulation models.

Figure 1:  AccelFPGA will let DSP designers develop their DSP algorithms in The MathWorks' Matlab environment and then synthesize the algorithms directly to a targeted FPGA architecture

Guiding the model's creation is what AccelChip calls a RDL file, which contains an architectural description of the FPGA that AccelFPGA targets. The DSP algorithm synthesis-into programmable-logic-hardware is thus similar to how a logic-synthesis tool creates a gate-level structural description of a circuit from an RTL architectural description, using information about a specific logic-cell library on which the tool bases its gate-level synthesis.

Advantages to the AccelFPGA flow are, along with a familiar design environment for DSP engineers (Matlab), are that DSP algorithm developers do not have to be conversant in Verilog or VHDL for generating the RTL model or the testbench—both are done automatically by the tool. Also, since AccelFPGA synthesis promises to be very fast, you can use it to analyze different algorithms, along with investigating area and performance tradeoffs during algorithm development, before committing to a specific FPGA. Furthermore, the tool has performance directives you can use to optimize synthesized algorithm performance, such as:

• Data streaming for single-rate and multi-rate systems
• Pipelining and unrolling of loops
• Sophisticated buffer and memory management
• Mapping to architecture-specific FPGA physical-execution units, such as multipliers.

AccelChip plans to make AccelFPGA available around September.

RF, Analog, and Mixed-Signal Design
Agilent and Cadence are combining their RF/mixed-signal design resources with the announcement of the RF Design Environment (RFDE). The environment integrates Agilent's RF frequency-domain simulation technologies into the Cadence analog/mixed signal design flow. The Agilent simulators include linear, harmonic balance, Circuit Envelope (time-swept harmonic balance), convolution (time-domain simulator that handles dispersive transmission line models and S-parameters), and HPSpice. Designers can also use Cadence's time-domain Spectre RF simulation for cross-domain verification.

Figure 2:  The RFDE environment integrates Agilent's RF frequency-domain simulation technologies into the Cadence analog/mixed signal design flow

RFDE also lets give designers access to Agilent's libraries of component and source models, including communication sources such as GSM, IS-95, DECT, and PHS. Other models include multi-coupled lines, active devices, custom models (equation-based), and S-parameters.

It appears that RFDE is Agilent's recognition of the company's inability to significantly impact Cadence's stronghold on the RF/mixed-signal chip design market. Instead of competing head-to-head with Cadence with its own design system, ADS, Agilent now seems content to place its own top-of-class point tools, such as ADS's frequency-domain simulators, into the Cadence design flow, increasing market share for these Agilent tools. Agilent expect RFDE subscription licenses to be available in October.

Also providing a boost for RF design is the Ansoft Designer tool suite for RF and high-speed simulation. With Designer, engineers can determine the electrical behavior of a device based on its physical attributes, without having to develop electrical models through measurement and creating equivalent circuits based on empirical fitting. The tool suite ties this electromagnetic modeling into a general circuit or system-level design environment with a direct link to layout.

The suite integrates electromagnetic, circuit, and system simulation, offering the following capabilities in one environment:

• Simulation for time, frequency, and mixed-mode analyses of circuits, systems, and components
• Modeling with advanced electromagnetic-field solvers for complete physical design
• A design flow with design entry, component management, and layout capability for chip, PCB, high-speed, and communication applications.

Ansoft Designer accurately characterizes chip structures affecting high-frequency operation, including spiral inductors, vias, and interconnects, and embeds them into the overall circuit or system simulation. The software also detects parasitic behavior, such as substrate coupling and chip-package-board interactions. For board designers, the tool uses customizable vendor-part libraries and electromagnetic solvers to help you understand the performance of circuits and subsystems of boards and modules, including surface-mount (SMD/SMT), chip-on-board (COB), flip-chip, ball-grid-array (BGA), and chip-scale-package (CSP) components.

Another announcement of interest to analog/mixed-signal chip designers is Barcelona's 0.13-micron version of the company's Miro synthesizable clocking engine. Designed to work with Barcelona's Prado synthesis platform (originally described in Analog Synthesis: Ready for Prime Time), Miro can synthesize and optimize multi-variant PLL designs from specification to a GDSII layout file. Available in July, Miro supports PLLs up to 1.8 GHz and jitter as low as 5 psec with a clock generation and synchronization, dual-voltage 2.5V/1.2V engine.

Custom Chip Design
Cadence has added several advances to its Version 5.0 custom chip design software, accounting for new digital/mixed-signal chip processes and providing improved chip-level integration. New features in Cadence's Chip Assembly Router give you a unified chip assembly environment, using shape-based routing technology, for merging large cell-based digital designs created within the company's SoC Encounter tool with custom digital, analog, mixed-signal, and RF blocks. Cadence has also expanded place-and-route capabilities for these blocks and for full-chip creation within the Virtuoso XL custom-layout editor. Other new features in the Chip Assembly Router include routing buses with bus interleave, crosstalk rules, pre-routes, power grids, and shielded-net topologies.

Additional advances within the Version 5.0 custom chip release focus on block-level productivity, yield predictability, and mixed-signal/mixed-language verification. Cadence has added VHDL-AMS to its existing Verilog-AMS simulation capability. Finally, the company has enhanced design-for-manufacturability (DFM) capabilities for CMOS-based analog circuits with yield-prediction technology from PDF Solutions.

For physical chip implementation, U.K.-based Pulsic has released its shape-based router, Lyric. Pulsic targets the current and future versions of the tool for several types of chip designs—digital, analog, mixed-signal, custom and SoC. Using a built-in extraction engine, Lyric does both timing- and signal-integrity-driven routing, taking into account antenna and crosstalk constraints. The router's shape-based engine can handle a variety of routing tasks, including global, detailed, power nets, and clock trees, with both automatic and interactive methodologies.

The current version of the tool, Lyric 2.0, handles a variety of design types but is not applicable to very large digital blocks—Pulsic expects to have this capability by the end of this year. Pulsic also expects to add by the end of 2002 channel routing (for top-level routing tasks), a topology editor, buffer and diode insertion (for antenna effects), and path-driven timing (the current version uses wire-based timing). Look for distributed computing support in 2003 to handle extremely large designs.

Virtual Prototyping
AXYS Design and Adelante have joined forces to develop a virtual prototype of Adelante's JPEG2000 reference platform. Adelante implemented the platform, comprising the company's Saturn DSP core, an ARM920T processor core, and two co-processors, in AXYS' MaxSim prototyping environment, a tool that lets designers model and verify multi-core SoC designs. Additional Saturn-based applications you can design with MaxSim virtual prototypes include 802.11, 3G, VoIP, and others.

Chip Debug
To attack the problem of debugging silicon samples prior to committing to expensive chip production, LogicVision has introduced Validator—a desktop diagnostics platform for at-speed debugging of silicon prototypes designed with the company's logic and memory embedded test software. With Validator, you don't need test vectors, test programs, and expensive test equipment, the latter normally engaged in production silicon testing.

Validator is part of LogicVision's design-to-debug methodology comprising software, silicon intellectual-property, and hardware. Upon receipt of first silicon prototypes, you use Validator, with its software and the design-for-test (DFT) database, to debug the prototypes. The debug platform contains two processors, a Sun SPARC and Pentium 3, and supports clocks up to 330 MHz. Validator supports JTAG data debug interfaces for chips and, optionally, for boards.