• Various design styles on a single chip (analog, mixed-signal, cell-based, full-custom)
• New device technologies
• Smaller process geometries with new design rules
• Lithography and manufacturing corrections
• Effects of long interconnects (antenna effects, analysis)
• Overall verification and analysis time.

Physical verification ensures that the physical design matches the design intent. New process and device technologies require more complex design rules. The demand for reduced iterations and decreased time-to-market results in the need to uncover and fix potential manufacturing problems, such as antenna effects and lithography aberrations, earlier during the physical-design cycle. Combining SoC modules with various design styles on a chip (including mixed-signal and full-custom) dramatically increases design size. A physical-verification and analysis flow needs to provide accurate solutions for these challenges, reduce the number of iterations involved in chip verification, and provide the fastest possible performance.

Today's large databases bog down traditional layout, debugging, and viewing tools. Opening a file may take hours and subsequent steps such as zooming, panning, and saving can be agonizingly slow. This is especially true if you are using tools that do not integrate adequately with the design environment. An inadequate tool may not only hamper the designer's efforts to produce a "clean" design, but may also cause a significant delay to the tape-out schedule. In addition, if multiple verification tools are used at the cell/block level, those tools will differ on the translation of clean data, which, in turn, could create integration problems at full-chip assembly.

Manufacturability checking is also typically done during the full-chip verification phase. The design has to be checked for metal density, and fill patterns are added in sparse areas of the chip. This added data might explode output-file sizes, which, in turn, can create a bottleneck at the mask-writer formatting stage.

To minimize output file sizes, it is critical to employ different extraction modes to the various components on a SoC. Analog modules must be extracted with the highest levels of accuracy, down to the transistor level. For digital macros, a gate-level extraction might suffice. Handling interconnect parasitics for the interfaces of the different modules is yet another consideration in SoC design. The challenge lies in determining and executing the level of extraction detail resulting in the highest accuracy, while enabling several extraction runs per day. Many extraction tools require the user to re-extract for each analysis output; that is, capacitance only, resistance plus lumped capacitance, and R-coupled-C. Multiple extraction runs for the various analysis modes take up valuable time.

Another issue is back-annotation of parasitic-extraction results. For parasitic netlists to be usable in the designer's simulation testbench, the extracted-layout netlist, including parasitic devices, needs to be back annotated to the schematic netlist. For transistor-level extraction, an LVS (logic vs. schematic) run is done to match layout devices and nets to the corresponding schematic. The parasitic-extraction tool has to be able to access the LVS data in order to produce the back-annotated netlist; therefore, a seamless interface between LVS and extraction is critical.

Stand-alone design groups using differing methodologies most often create individual components of a SoC. At a time when as much as seventy-five percent of a designer's efforts can be spent on verification issues, additional verification steps created as the result of not using the foundry standard can determine whether or not a product meets the time-to-market schedule or first-working silicon opportunity.

Figure 1:  A single-tool physical-verification flow achieves cycle-time reduction in SoC designs

A physical-verification system that is well integrated into a custom-layout environment may greatly boost productivity at the modular level. Integration involves automation of common tasks such as stream-out, netlisting, and graphical debugging, along with a cross-probing environment where errors can be viewed and fixed in the actual layout. To save further iteration time, only corrected areas of the design need to be re-verified. During verification, the layout environment is not "locked," and the designer can use the layout tool for different tasks.

An intuitive graphical user-interface (GUI) is at the center of an efficient verification environment. Such an interface provides access to cell/block level verification as well as full-chip verification. A single rule-file for both cell/block verification and full-chip verification ensures that all components of a design, as well as their interactions, are accurately verified, with no chance for missed errors. Locating top-level signal shorts with traditional tools, or manually, can possibly delay a tape-out for weeks. Using a production-proven verification environment, you can locate and fix shorts in a matter of minutes.

The verification interface is also the center of integration for all other backend verification functions. Within such an interface, the designer can launch parasitic extraction and back-annotate parasitic values to the actual design environment. Shared algorithms and shared rule-files between tools, such as LVS and parasitic extraction, save significant steps and time in the verification flow. All parts of the flow, from DRC through extraction, can use multi-threaded processing to maximize performance. The look and feel of the various applications is the same, so the time to adopt, integrate, and master the tools is greatly reduced.

Figure 2:  All parasitic data is stored and on-call in the extracted database. All data critical for downstream analyses can be stored in netlist formats as needed without having to rerun extraction

A hierarchical netlist can further streamline the post-layout analysis flow. Hierarchical netlists enable complete full-chip transistor-level simulations in hours with powerful full-chip SPICE simulation tools on the market. Parasitic extraction for SoCs needs to address the added data volume of fill patterns. Fill polygons of various metals are added to sparse areas of the chip before manufacturing in order to help in planarization of the wafer surface. Due to the vast data volume resulting from the flat metal-fill methodologies of other verification tools, parasitic extraction including metal-fill used to be a bottleneck. Yet, the inclusion of metal-fill patterns is critical for accurate parasitic extraction. In a streamlined SoC verification flow, metal-fill data can be added and arrayed hierarchically during the DRC stage, and automatically handled by the extractor as intrinsic or coupling capacitors. Therefore, the bottleneck is eliminated.

To provide meaningful input to analysis, the parasitic netlist has to fit seamlessly into the designer's simulation environment, which is typically in the schematic source environment. Therefore, you need an LVS comparison of the design, which stores a cross-reference database of devices and nets. The extractor then can access this data and merge it with the parasitic results. Simulation and analysis tools can now use the merged netlist, containing designed devices and nets as well as all parasitic information. This example illustrates the extreme importance of seamless tool interfacing.

Selecting the foundry's internal, or "golden," physical-verification standard ensures command files are readily available, up to date, and fully supported. Without this reliable standardization, designers have to construct their own rule files, or "fix" the design according to the foundry's internal physical-verification standard, which exposes designs to a greater risk of costly and time-consuming error-correction cycles.

About the Author Claudia Relyea holds a B.S. in Electrical Engineering, and has an extensive background in analog design. For the past three years, she has worked in technical and product marketing focusing on physical verification and parasitic extraction. She joined Mentor Graphics in 2002 as technical marketing engineer for the Calibre parasitic-extraction product line.