A perennial highlight of the Spring slew of technical conferences is the Custom Integrated Circuits Conference (CICC). This year's CICC takes place in Orlando, Florida from May 12-15. The conference brings together top-notch educational sessions, informative panels, outstanding papers spanning a wide range of technical topics, and an exhibit area showcasing the latest chip products and services. Rounding CICC's 'Innovation, Education, Communication' theme are interesting and entertaining Keynote and Luncheon speakers.

The conference starts on Sunday with three parallel all-day educational sessions. This year's topics are:

1. Advanced RF: From Devices to Systems
2. Advanced Data Converter Design and Test Techniques
3. High-Performance and Low-Voltage Design Challenges and Techniques.

These topics mirror some of the hottest segments of the electronics industry—wireless systems, interfacing analog/digital circuitry, and designing portable devices. Each session comprises four two-hour modules presented by well-known industry and university experts.

CICC's panels have always been recognized for their timely and, often, controversial topics—this year is no exception. Taking place on Tuesday, you have the opportunity to attend one afternoon panel, Design Challenges in Wireless LANs (and the WLAN winner is?), and two evening panels, Will the Next Great Killer Technology Application Please Stand Up! and Can Scaling Continue at the Same Rate Below 0.1um? What is the End of CMOSand What is Next? The WLAN panel should be very entertaining, providing an opportunity for 802.11 and Bluetooth proponents to "square off" over issues such as process technology, system architectures, RF-baseband integration, and the feasibility of combining both technologies on one chip. The Killer Apps panel will feature industry luminaries trying to solve the "chicken and egg" quandary of technology and applications for that technology. As for the scaling question, when will we see the end of silicon as we know it? Silicon's scaling limit keeps moving out, from a 100nm limit predicted by some around 1990 down to as low as 35 nm and beyond proposed by certain experts today. New device architectures and photolithography advancements push silicon's limits—but will we be ultimately limited by other factors, such as manufacturing cost, design tools, and power dissipation?

The technical sessions at CICC are always a highlight of the conference, consistently given high marks by the conference attendees. This year, CICC technical session chairs have identified several papers that they feel are particularly outstanding.

• Paper 2-3: A Reconfigurable System Featuring Dynamically Extensible Embedded Microprocessor, FPGA and Customisable I/O
  An excellent example of SoC design and the use of technology blending, this paper is a nice example of a high-level design from C/C++.
  
  
• Paper 3-4: A Multi-objective Design Space Exploration Tool for Analog and RF IC Design
  The optimization technique not only provides optimized circuits for a set of specifications, but also provides tradeoffs between competing objectives during performance optimization. The ability to do design space exploration is quite unique.
  
  
• Paper 4-1: Integration and Systems Design Trends of ADSL Analog Front Ends and Hybrid Line Interfaces (Invited)
  A complete overview of the current status of ADSL analog front-ends addressing design issues, hybrid-design challenges, and various line-driver techniques for low-power applications.
  
  
• Paper 5-1: An Architecture for a Programmable Mixed System Device
  A mixed-signal, field-programmable SoC device integrating a microcontroller, flash memory, SRAM, programmable analog and digital blocks, along with on-chip clock generation.
  
  
• Paper 6-1: A Deep Sub-Micron Timing Measurement Circuit Using a Single-Stage Vernier Delay Line
  This is a novel circuit for embedded test, implementing timing and jitter measurements with a resolution of greater than 1 GHz. The circuit was implemented in a 0.18 mm process and was shown to be insensitive to component mismatch. The area reduction was significant compared to previous approaches.
  
  
• Paper 7-1: A Simple 1-T Capacitorless Memory Cell for High Performance Embedded DRAMs
  This paper proposes a novel capacitor-less embedded DRAM by exploiting the system-on-insulator (SOI) characteristics. The proposed eDRAM SOI technology demonstrates production feasibility and new memory paradigms.
  
  
• Paper 8-3: 4 Gbps High-Density AC Coupled Interconnection (Invited)
  A unique and novel way to keep up with Rent's rule as chip dimensions continue to scale down.
  
  
• Paper 9-1: A 2.29 Gb/s 56mW Non-pipelined Rjindael AES Encryption IC in a 1.8v, 0.18 mm CMOS Technology
  This is an on-the-fly scheduling, high-performance, single-chip solution for 2.29 Gbits/s Rjindael AES encryption with ultra-low-power consumption of 56 mW. The chip is fabricated in a 0.18 mm CMOS technology.
  
  
• Paper 9-4: A Vector DSP for Imaging
  This describes a DSP with a novel vector architecture. The architecture exploits the parallelism and narrow data typical of image processing to obtain high performance at low cost and power. The DSP runs at 200 MHz (worse case) and can do sixteen 16-bit MACs/cycle along with 32-bit memory accesses per cycle to 128 Kbytes of on-chip memory.
  
  
• Paper 11-3: Virtual Damping in Oscillators
  The author presents a new and novel perspective on noise in oscillators.
  
  
• Paper 12-4: Analysis and Optimization of IIP2 in CMOS Direct Down-Converters
  Discussed key parameters for direct-down converter.
  
  
• Paper 13-3: High Dynamic Range CMOS Image Sensor with Conditional Reset
  This paper proposes a new pixel structure to increase the dynamic range and the signal-to-noise ratio for CMOS image sensors.
  
  
• Paper 18-1: A Design Methodology for Low EMI-Noise Microprocessor with Accurate Estimation-Reduction-Verification
  EMI (electromagnetic interference), a relatively new concern for chip designers, is addressed early in the design cycle in this paper. The authors propose an accurate EMI noise modeling and simulation methodology at a gate-level design representation.
  
  
• Paper 20-1: A 10Gbase Ethernet Transceiver (LAN PHY) in a 1.8V, 0.18mm SOI/CMOS Technology
  The authors present the design and experimental results of a 10-Gbit Ethernet transceiver, utilizing a high-speed interface and fully integrated IEEE 802.3ae compliant logic. Fabricated in a 0.18-mm SOI/CMOS process, the transceiver consumes 2.9 W of power from a 1.8-V supply.
  
  
• Paper 21-1: Integrated Circuits for 3GPP Mobile Wireless Systems (Invited)
  This paper provides an excellent overview of the computational challenges of 3G along with a description of chip architectures for base-band processors in 3G mobile wireless systems. The paper also includes state-of-the-art examples of 3G base-station chips.
  
  
• Paper 22-2: A 1-V 0.9dB NF Low Noise Amplifier for 5-6 GHz WLAN in 0.18um CMOS
  This is an implementation of a low-noise amplifier for WLAN applications. A very low noise figure was achieved in the 5-6 GHz band with a low supply voltage using transformer feedback.
  
  
• Paper 23-1: A 1.8V Fully Embedded 10b 160 MS/s Two-step ADC In 0.18mm CMOS
  This ADC pushes the state-of-the-art for low-voltage (1.8V) operation by achieving 10-bit performance at 160 MS/s with a power dissipation of only 190 mW. The device uses interpolation to achieve small die size and low power dissipation.
  
  
• Paper 24-4: High Speed, Low Power, Optoelectronic InP-based HBT Integrated Circuits (Invited)
  This tutorial is a comprehensive review of the materials, process development, circuit-level, and system-level issues for circuit designers unfamiliar with Indium Phosphide (InP). This emerging, scalable technology can enable communication speeds beyond 40 Gbits/s by improving the performance of key "bottleneck" components.
  
  
• Paper 25-6: Comprehensive Study of Energy Dissipation in Lossy Transmission Lines Driven by CMOS Inverters
  Interconnect performance and power consumption are critical issues in ultra-deep submicron design. A good approximation of Telegrapher's equation is presented, enabling the study of the effects of lossy transmission lines on circuit implementations.
  
  

Rounding out the key CICC events are the always-popular keynote and luncheon speakers. Opening this year's conference is AMI Semiconductors' recently appointed CEO and President, Christine King. Ms King's Monday morning's address, Smart Management of ASIC Requirements and Technology (SMART), will focus on several of the complex issues facing the semiconductor industry, such as time-to-market, productivity, cost, performance, and power. The talk will discuss the idea of combining several chip implementations—including medium-density ASICs, standard products, and FPGAs—to meet non-leading-edge applications, along with leading-edge ASICS for high-end, architecture-specific use. Tuesday's conference luncheon features Dr. Eugene Trinh, Director of the Physical Sciences Research Division in NASA's Biological and Physical Research Enterprise. Dr. Trinh's talk, Science in Space: Accomplishments and Promises of Research in Low-Gravity, calls on his experiences aboard the Space Shuttle Columbia along with his research background for a presentation of current and low-gravity work in several technology arenas.

If the upcoming CICC sounds interesting, exciting, educational, and even a bit overwhelming—it is! Butif you are involved in chip process-development, or in chip and chip-based system design, evaluation, and test, Orlando is the place to be on May 12 to learn about the latest and greatest advancements in this fast-moving industry. Find out more by visiting www.ieee-cicc.org.