New Devices, Design Tools Fuel Programmable Logic Resurgence

Jim Lipman

3/28/2002 12:00 AM EST

The past few months have seen an increase of announcements from programmable-logic hardware and design-tool vendors touting significant product introductions and enhancements. First came Altera's February announcement of Stratix, a CPLD architecture that benefits from an ASIC-like, block-based design methodology and allows design-team members to independently design various functional blocks. In March, both Xilinx and Altera brought out new products addressing configurable SoC (CSoC) design while Mentor Graphics and Actel announced new or enhanced programmable-logic design tools.

Common to these announcements is that designing state-of-the-art programmable-logic devices is becoming more "ASIC-like". Designing an FPGA or CPLD with an ASIC methodology is essential for the latest programmable logic families, particularly those families containing embedded silicon cores. Many of the design and verification problems seen by designers of these high-speed, high-density programmable chips are similar to the problems encountered by an ASIC or SoC designer. High-speed timing, signal integrity, thermal, and routing issues"not prevalent in programmable-logic design a few short years ago"are cropping up with regularity on multi-million-gate FPGA and CPLD designs running at hundreds of megahertz. This has led to a change in the way programmable-logic hardware and software vendors develop new device families and design tools.

What's New
Xilinx's Virtex-II Pro family combines PowerPC RISC processor cores with multi-gigabit serial transceivers on an FPGA chip. Virtex-II Pro can handle up to four PowerPC 405 hard cores, each running up to 300 MHz, anywhere in the FPGA fabric, with the high-speed core buses coupled directly to the fabric. Along with the cores, Virtex-II Pro has a 3.125 Gbit/s serial interface, based on Conexant Systems' SkyRail technology. The technology, which Xilinx calls RocketIO, supports high-performance interface standards such as Gigabit Ethernet, 10 Gigabit Ethernet, 3GIO, SerialATA, Infiniband, and FibreChannel.

Along with the Virtex-II Pro family, Xilinx also has a comprehensive set of products for software development, hardware development, and system integration, including compilers and integrated development environments (IDEs) from Wind River and GNU. Xilinx's System Generator for PowerPC tool lets you build custom PowerPC processor systems with Virtex-II Pro, helping designers architect, customize, and generate the hardware and software components for an entire processor system. Hardware debug options are also available from Wind River and Agilent Technologies.

Also addressing silicon IP (SIP) integration into a programmable-logic fabric is Altera's SOPC Builder. SOPC (System on a Programmable Chip) is Altera's term for a configurable CPLD-based device. SOPC Builder automates the job of parameterizing silicon cores and then embedding these cores into a CPLD. The tool lets you select and parameterize SIP components from an available drop-down list of communication, DSP, microprocessor, and bus-interface cores, or you can also use your own SIP. SIP is available from Altera and members of AMPP, the Altera Megafunction Partners Program. The SIP customizing is core-specific and may include both hardware and software parameterization.

SOPC Builder then helps a designer generate a synthesized netlist, simulation testbench, and custom software library reflecting the target hardware configuration. The tool automatically generates system software that matches the target hardware, along with the testbench. You use SOPC Builder with Altera's Excalibur embedded processor products to create a configurable SoC that includes on-chip memory, processor cores, I/O functions, and application-specific SIP. SOPC Builder handles intra-chip communication with the AMBA-AHB bus, a bus standard for SoC chips using an ARM processor, along with Altera's Avalon bus supporting the company's library of Nios soft-processor core peripherals.

Other programmable-logic software developments include Actel enhancing its FPGA design suite and Mentor with a new programmable-logic synthesis tool. Actel has updated Libero, the company's IDE for supporting ProASIC Plus flash-based devices. The enhanced design tools let designers take advantage of ProASIC Plus features such as higher densities, multiple PLLs, in-system programmability, increased memory, and user-configurable I/Os. In addition, free Libero Silver and Platinum evaluation versions are now available at www.actel.com. Libero includes tools for schematic capture, HDL entry, testbench generation, simulation, synthesis, place-and-route operations, and logic analysis. Libero Silver supports devices up to 10,000 gates, but does not include a simulator. Libero Platinum features unlimited design capability. The Platinum evaluation version has all the capabilities of the full Platinum tool minus a programming function.

Mentor Graphics debuted Precision Synthesis, a synthesis tool for both traditional and CSoC versions of FPGAs and CPLDs. Mentor targets the tool for leading-edge programmable devices such as Altera's Stratix and Excalibur architectures and Xilinx's Virtex-II Platform FPGAs. Precision Synthesis, intended as a replacement for Mentor's for LeonardoSpectrum level-three customers, comprises an intuitive GUI, a new suite of optimization algorithms (ASE optimization) and PreciseTime, a new timing engine.

The tool's Design Center is a synthesis "control room" from which a designer performs operations such as adding or editing design and constraint files, viewing synthesis and place-and-route report files, and doing revision management tasks, such as controlling design iterations. Architecture Signature Extraction (ASE) optimization focuses specific optimizations on areas of the design that might impact overall performance, such as finite-state machines, cross-hierarchical paths, or paths with excessive combinatorial logic. The optimization performs advanced tasks such as Look-Up Table (LUT) merging, logic tunneling, register re-timing and timing-driven I/O block (IOB) mapping to achieve desired performance without iterative manual user intervention. PreciseTime is an incremental timing engine with features similar to those available in a stand-alone static-timing-analysis tool. The tool automatically isolates critical timing-path violations. After identifying the critical timing paths, Precision Synthesis invokes ASE optimization to repair all marginal timing problems prior to programming the FPGA. PreciseTime also provides advanced constraint-driven timing analysis, letting you modify design constraints on critical paths and immediately view the results of the modification.