The annual electronics design-tool Mecca known as the Design Automation Conference (DAC) took place the first week in June, accompanied by the collective finger crossing of EDA tool vendors and customers alike. The still stagnant economy, coupled with apprehension regarding SARS, made the event a relatively low-key affair. Total show attendance was up around 7% from last year, to a little over 10,000 people, while the number of exhibitors increased 18% to 213.

Like the conference mood itself, product news at the show was at a relatively low level. Announcements primarily dealt with enhancements to existing products and services, along with the usual technology agreements between vendors. However, there were a few EDA vendors touting new or updated products of some significance.

Cascade synthesizes a co-processor that runs user-identified tasks, via application software, originally run by the main processor. The tool suite does this by using techniques to analyze the code to be off-loaded and using an innovative micro-architecture to implement the co-processor. The result is a co-optimization of both the processor and the software it runs. The synthesized co-processor is task-specific, which means that it is optimized to do the tasks you want to offload from the main processor. This allows the main processor to take on additional tasks, such as those that might be associated with an enhanced feature set of a camera or cell phone, or to run an existing set of tasks more efficiently (either faster or with less power).

Figure 1:  By synthesizing design-specific co-processors to run tasks originally done by the main processor, Cascade frees the main processor to either do additional work or run current jobs more efficiently.

The way Cascade operates is different from other processor-function synthesis tools, such as those In Celoxica's DK Design Suite. Cascade works on existing HW/SW systems, allowing them to work more efficiently or to expand their capabilities. DK compiles Handel-C, a high-level C-like system specification, into hardware implementations (FPGAs and embedded processor cores) of system algorithms, without going through an intermediate HDL step. You thus use DK for new system development and Cascade for enhancing existing systems.

Along with the co-processor RTL code, the Cascade tools also generate a cycle-accurate C-model of the co-processor, which lets you analyze its performance in a native system environment. You can also do "what if" analyses of different combinations of off-loaded tasks to determine which ones to run on the synthesized co-processor. The tool suite also lets you verify co-processor hardware and its associated microcode against the original software's functionality running on the main processor, and generate co-processor RTL code for implementation and for supporting other user-defined hardware functions.

Moving to the physical-implementation side of chip design, Bristol U.K.-based Pulsic announced Prelude, a new family of shape-based, high-capacity layout tools. Pulsic designed its previously released Lyric Physical Design Framework for routing and ECO placement of analog, custom, mixed-signal, chip assembly, and small digital designs. The Prelude family's first product, Prelude ECO, on the other hand, is for very large digital designs, specifically for late-stage ECO placement and routing, complementing popular mainstream place-and-route (P&R) tools. Prelude ECO's capacity is huge—around 10M nets, equivalent to about 25M logic gates. The tool also supports a true heterogeneous, distributed computing environment and has a very low memory footprint, handling one-million cells worth of fully routed data per Gbyte of memory. Additional Prelude ECO features include a built-in 2D extraction engine for timing and signal-integrity closure, and support for Chartered and UMC 130nm processes, including slotting and 45-degree/free-angle routing rules.

Pulsic enters a market—large-capacity IC physical design—dominated by two EDA players, Cadence and Synopsys (from its Avant! acquisition). However, by addressing a niche in this market for the first Prelude product—ECO implementation—Pulsic gets a foot in the physical-implementation door where they might make a strong impact. Pulsic plans future Prelude products for other chip P&R operations.

DAC also provided a coming-out party for ChipMD, whose products provide design-for-yield (DFY) tools you use during the design phases of RF, analog, and mixed-signal chips, as well as memories and digital libraries. The company's tools let designers analyze and estimate a chip's parametric yield at the transistor level, early in the design process, allowing the designer to optimize for maximum yield. Most design-for-manufacturability (DFM) tools that address yield do so late in the design process, after placement and routing. ChipMD tools use sensitivity and deterministic mathematical analyses, differentiating them from yield estimation and statistical tools, and fit in existing design flows. With their DFY tools, the company boasts 20-50% reductions in cost and time to market, up to a 50% increase in performance, and 20% design-yield improvements.

Roger Carpenter, a senior engineering manager at Broadcom, sees the front-end/backend view of chip design as obsolete. Carpenter feels that designers should look at chip design as they do system design, going from specification to implementation. His concept also fits in with the idea of RTL signoff in SoC design, where the design's specification and architectural development takes place entirely at RTL. RTL specification is then followed by chip implementation merging synthesis and placement, along with design-for-test (DFT) and clock-distribution design, and pre-silicon full-chip prototyping.

Magma's VP of front-end engineering, Arvind Srinivasan, also dislikes the current flow from logic synthesis to physical implementation. He feels that front-end optimizations, in logic or physical synthesis, represent wasted effort, since these optimizations are redone during P&R and done better since they have available more accurate physical information. Srinivasan also feels that front-end optimization provides no timing-closure predictability, since critical nets may change during and after placement and routing.

Eric Filseth, marketing VP at Cadence, shares some of the same views as Srinivasan. Filseth thinks that RTL synthesis should focus on architecture with the back-end tools accomplishing timing closure. He also would like to see more use of global-synthesis architectures, which optimize logic specifically for its overall interconnect structure. Filseth states that such architectures enable significantly faster chips, from the same RTL, than you can get using older synthesis architectures. Obtaining a faster chip using this method also fuels the argument for RTL signoff.

Drew Wingard, Sonics' CTO, thinks the front-end/backend handoff boundary has been broken for some time, since traditional design tools and flows are gate-centric rather than wire-centric. Architectures don't really understand physical design and if wire-induced delays exceed design cycle times, no amount of front-end architecture redesign will solve the problem. Wingard proposes a MicroNetwork-based chip architecture to de-couple communication from computation. He feels this move would improve interconnect-delay management at all design levels and let designers validate the physical properties of the architecture very early in a design.

At its founding, SPIRIT comprised the following companies:

• ARM—SIP provider who will help drive standards requirements and priorities
• Beach Solutions—developer of XML-based IP packaging and integration tools
• Cadence—EDA vendor of system-level design tools
• Mentor Graphics—EDA vendor contributing the company's Platform Express XML Component Schema technology
• Philips Semiconductors—Integrated Device Manufacturer (IDM) who will test developed standards throughout the full SoC development cycle
• ST Microelectronics—IDM who will do standards testing and provide user input to standards development
• Synopsys—EDA vendor offering tools for delivering and configuring synthesizable SIP cores.

The consortium expects to have a pilot-program-validated proposal for the standards by the end of 2003, with a general release sometime in early 2004.

Jim Lipman is a consultant providing marketing, writing, and other electronics industry services, specializing in EDA tools and ASIC/SoC design methodologies. His job experience includes chip-design R&D, marketing, marcom, technical editing, and on-line publishing of technical content for engineers.