New IP Integration Strategies Simplify SoC Design

Silicon-intellectual-property (SIP) cores can offer a tremendous advantage to designers building complex system-on-a-chip (SoC) devices. By acquiring pre-built functions, designers can shorten design time and focus on the application—providing value-added elements that emphasize the design organization's application expertise and corporate competencies. Yet, in attempting to work with multiple SIP cores, the SoC designer too often faces integration and verification difficulties that negate any anticipated savings of design time. Indeed, SoC designers find they need several months or more to integrate third-party silicon cores into complete systems and verify the integrated system-level design. To work with the variety of cores in the market today, designers need to focus on a specific strategy for managing SIP interconnect to ensure efficient integration and system-level verification.

In conventional systems development, designers rely on standard buses such as VME, PCI, and others to interconnect individual subsystems. Subsystem designers build bus-arbitration logic within each subsystem to manage the well-defined master/slave transactions across the bus. In turn, system integrators rely on compliance with the standard bus protocol to ensure that they can quickly and reliably integrate compliant adaptors from multiple sources into systems.

Bus-Based Approaches
Bus-oriented approaches from the world of standard components and printed-circuit boards do not translate successfully to SoC design. Bus-based approaches are simply not appropriate for SoC design due to the overhead imposed by bus-arbitration, bus width, split transactions, bursting, pipelining, and tri-state logic. In SoCs, the existence of these additional logic circuit elements—and associated logical states—significantly complicates design, synthesis, and verification. Because third-party IP vendors do not build bus specific logic into cores, the SoC designer must allocate time and silicon resources to design in the additional circuitry. The design also must address the additional logic states available with bus structures during system-level verification.

SoC designers face a basic paradox in today's environment: rather than enjoy significant time savings in using acquired cores, they need to spend additional time learning circuit function to build the logic and test vectors for these cores. Indeed, other than processor core vendors, IP vendors typically provide little of the detailed documentation designers need to learn these details. Consequently, designers find they have to acquire some level of application expertise or additional consulting resources to understand the SIP function well enough to complete these tasks. This additional design and verification burden currently adds months to SoC design projects. Besides imposing a drain on resource-strapped projects, the additional logic inevitably degrades performance and area, while the additional test requirements further complicate final test stages.

SoC Approaches
The industry is in general approaching the SIP interconnect problem from two different tacks—one intended for SIP developers (those who build cores) and the other for SoC developers (those who build with cores). For SIP developers, vendors have proposed a variety of on-chip bus-interface definitions in the hope that IP developers would adopt their particular definition and build in the necessary logic needed to conform to that bus. For SoC developers, SIP providers have suggested different methods intended to wrap cores with glue logic—leaving the SoC developer to deal with any degradation in area or performance and with increasing test requirements.

To reduce the impact of these problems, companies have proposed various bus interface definitions, such as ARM's ABMA and IBM's CoreConnect, as common interconnection schemes. Furthermore, the Virtual Socket Interface Alliance (VSIA) industry consortium was established in the mid-1990s to determine standards for designing and integrating reusable SIP, which VSIA calls Virtual Components (VC). The VSIA soon realized, however, that legacy cores tied to existing bus definitions would limit the organization's ability to select an existing bus or define a new standard bus. Consequently, the consortium decided to define a VC interface (VCI) for designers to use as a point-to-point connector or as an interface to a bus-interface module. The more recent appearance of SoC development platforms has further helped eliminate concerns over legacy cores and diverse interfaces.

Avoiding Bus Approaches
Because of the need for additional logic for bus-arbitration, bus width, split transactions, bursting, pipelining, and tri-state bus structures, bus-oriented approaches will inevitably impose additional test demands. These approaches constrain the designer's ability to minimize area and maximize performance. In contrast, there are emerging bus-less approaches to simplify core integration and system-level verification.

In one approach, SoC designers use channels to link cores. Channels date back to traditional system architectures, such as IBM mainframes, where they provided a mechanism to connect peripherals such as mass storage. The concept behind these channel-based approaches translates well to SoC development: instead of forcing the use of bus structures, channel-based mechanisms can simplify high-throughput connections such as those between processor cores and memory blocks. In most SoC-based embedded systems, the object is to receive the data into the memory at the input peripheral speed, process it as quickly as possible, and transmit the processed data from memory at the output peripheral speed. The availability of high-bandwidth channels for input, output, and processor to the memory not only meets the system requirements but also simplifies the SoC design, integration, and verification.

Another important interconnection method uses dedicated point-to-point connections between cores. In this approach, SoC designers form dedicated connections between individual cores that need to interact. In theory, designers can use connection strategies such as star topologies that link every block with every other block. In practice, however, star topologies impose excessive interconnect requirements and are not ideal for SoC designs. In fact, designers do not need to use star topologies, since the critical connections are those between processor, memory, and peripheral cores. Consequently, a point-to-point approach is particularly suited for providing dedicated one-to-many connections between a processor core and each individual peripheral core. This point-to-point approach allows multiple designers to work simultaneously—each designer can integrate his or her block in the SoC and perform hardware/software co-verification independently, simplifying design verification and debugging.

Channel-based and point-to-point interconnection methods share an important feature—neither requires significant circuit overhead to deploy, nor does either levy a significant burden in verification tasks. Most important, the combination of channel-based and point-to-point methods is well suited to interconnecting bus-based cores. For these cores, designers can use point-to-point connections to handle control functions such as register access and transaction execution, while using channels to link the core to memory for high-speed direct-memory access.

Finally, the new bus-less integration architectures help speed system verification—by as much as 50% based on current experience. Along with simple interconnection mechanisms based on channel and point-to-point approaches, leading development platforms embed a consistent verification approach throughout the SoC design process.

Integration Architectures
More recently, SIP vendors have begun combining pre-integrated, pre-verified silicon cores with an integration architecture to provide a complete development-platform package. Development platforms, such as those from Palmchip and other vendors, provide all the SIP needed for specific types of applications as well as channel-based and point-to-point interconnect mechanisms needed to integrate additional cores.

As the foundation for SoC design, development platforms are typically available in two basic types: general-purpose and application-specific. General-purpose development platforms contain all the peripheral functions required for a basic SoC. Available cores may include pre-verified, integrated peripheral functions—such as system and watchdog timers, interrupt controller, programmable I/O, memory controller, DMA controller, and UART—as well as various pre-verified processor cores from ARM, MIPS, ARC, and other processor-core vendors. Using this type of general-purpose processor-based platform, a designer can build an SoC to meet specific system requirements using the cores needed for that particular system along with an appropriate interconnect mechanism.

In some cases, however, certain types of applications require specific functions. Application-specific development platforms serve this need by combining the pre-built and pre-verified SIP required to meet those exact requirements. Just as silicon cores deliver design expertise for particular functions, application-specific development platforms deliver system-level design expertise for particular application segments. Using this approach, SoC designers can start with tuned development platforms, such as disk drive controllers, smart card controllers, printer controllers and multimedia controllers and add additional custom SIP to meet product requirements.

As product lifecycles shrink in today's competitive marketplace, SoC designers face a tremendous challenge in delivering working first silicon on time and on budget. Although silicon cores hold promise for delivering the needed boost in productivity, designers need a core-interconnect strategy that facilitates integration and system-level verification. Newer strategies based on channel-based and point-to-point interconnect mechanisms promise to dramatically simplify the integration and verification of multiple cores in complex SoCs. By embedding a bus-less interconnect architecture with SIP in ready-to-use development platforms, core providers are beginning to help SoC designers gain the development edge they need in the face of spiraling requirements and shrinking schedules.

About the Author

Robin Bhagat, vice president, SoC technology, is responsible for SoC embedded-software development and hardware/software co-design methodology at Palmchip. He has seventeen years of experience in the embedded systems industry, with experience in system-level engineering, embedded products, and SoC development.

Prior to Palmchip, Bhagat worked at Bay Networks, Adobe Systems, Quantum, and Xerox in various engineering positions. He has authored numerous articles, and has presented papers at various conferences. Bhagat graduated from Bombay University with degrees in Physics, Mathematics, and Electronics Engineering, and received his master's degree in Computer Engineering at Santa Clara University in California. Bhagat is currently chair of the VSIA Verification Development Working Group.