Configurable SoCs Give You Options

System-on-chip (SoC) designs, with their high-performance, high-density promises, are not developing as rapidly as some proponents have predicted. High cost and longer-than-desired time to market have limited SoCs to the high volume segment of the chip industry. Enter the configurable SoC (CSoC), with its ability to meet evolving standards and accept design changes late in the development cycle, and you have a new breed of chip that is becoming very attractive to many system developers.

The siren song of SoC design is a chip that combines high performance with minimum silicon area, which translates to low cost. The obstacles to SoC design are high development cost (NRE), high design complexity, and long development time. The combination of these feature sets makes today's SoCs attractive for high volume, high-complexity system design, but not for low-to-middle volume applications. Another barrier to SoC design is the cost of redoing the design if first silicon is tested and found to not meet specifications. A design error or specification change due, for example, to a change in a communication standard, can result in a very expensive silicon re-spin (new masks and a new process run). A 0.18-micron mask set runs around $250,000, a cost which, when added to the delay needed to fabricate new silicon, can result in a loss of millions of dollars in potential product revenue.

The first developer of CSoC products, Triscend, has two product lines"the 8-bit E5 and 32-bit A7. The company introduced the first CSoC family, the E5, in October of 1998. Based on an enhanced version of the 8-bit 8032 microcontroller, the E5 is a four-device family with similar architecture, but different amounts of programmable logic, SRAM, and I/Os. The E5 operates up to 40-MHz and offers 10-MIPS performance. E5 chips have up to 64-Kbytes system RAM, up to 3200 CSL cells (about 40K logic gates), and use an internally-developed bus, CSI (Configurable System Interconnect). CSI has a data-transfer rate up to 40-Mbytes/sec and comprises a 32-bit address bus and 8-bit data bus. For use with the 8032 core, Triscend's FastChip software includes an IP library of soft microcontroller peripherals including timers/counters, programmable I/O, UARTS, and FIFOs.

In mid-2000, Triscend extended its CSoC offering with the ARM7TDMI-based A7 family. The 32-bit ARM core includes cache memory, a four-channel DMA controller, external memory interface, and advanced debug capability. The A7 also uses common microcontroller-peripheral soft cores from Triscend's FastChip library. View the A7 CSoC block diagram.

Altera refers to its Excalibur products as embedded-processor components. The company gives you a choice of different microprocessors in Excalibur chips. To date, Altera has announced three processor cores: the homegrown Nios soft core and both ARM and MIPS 32-bit hard cores. Nios, according to Altera, was explicitly developed for the company's programmable-logic architectures, specifically its APEX family. Altera considers the APEX architecture, currently on a 0.18-micron, six-level-metal process, to be its main SOPC platform. A Nios core takes around 1100 logic elements (each logic element is a four-input look-up table plus a flip-flop). Nios features a 16-bit instruction set, 16- or 32-bit datapaths, and a five-stage pipeline averaging one instruction per clock cycle and up to 50-MIPS performance.

Figure 2: Embedded in an APEX PLD, the Nios soft core consumes little area but provides up to 50 MIPS performance. Customizable peripherals include a UART, timer, Parallel I/O, and memory.

The XA (ARM922T-based) and XM (MIPS32 4KC-based) versions of Excalibur run at clock rates up to 200-MHz. Both the XA and XM use the AMBA AHB (Advanced High-performance Bus) as an interface between the embedded-processor cores and the programmable array. AMBA is an open standard, on-chip bus featuring multiple bus master support and pipelined burst transfers. The ARM core includes a memory-management unit (MMU), along with 8-Kbyte data and instruction caches. Altera embeds the core into a fully diffused area of the APEX array, along with up 256-Kbytes of SRAM, 128-Kbytes of dual-port RAM, and various controllers, external bus interfaces, counters, and trace/debug logic. The MIPS core has 16-Kbyte instruction and data caches, a multiple/divide unit, and resides in a diffused APEX region similar to the region configuration for the ARM core.

In Excalibur's XA family, the ARM core is located in a fully diffused area of the APEX chip along with cache memory, peripherals, and debug logic (figure 3). Different XA family members have varying amounts of additional memory.

The recently announced Xilinx Platform FPGA initiative is an ambitious embedded-system development effort. Platform FPGA encompasses three communication-centric technologies: processing (Empower), DSP (ExtremeDSP), and system-level communications (SystemIO). Xilinx is defining its CSoC chips as combinations of both soft and hard silicon cores embedded into Xilinx's Virtex-II architecture. The company has developed two technologies to assist in Virtex-based CSoC design. The first, IP Immersion, lets you place hard silicon cores anywhere in the Platform FPGA fabric. The second, Active Interconnect, describes actively driven routing channels for predictable core performance wherever the cores are located in the array.

At this time, Xilinx has announced only one microprocessor hard core, the IBM PowerPC 405. The 405 core runs at 300-MHz and supplies 420-MIPS of processing power. For on-chip busing and core interconnect, Xilinx is using IBM's CoreConnect bus architecture. CoreConnect is available in 32-, 64-, and 128-bit versions, operates up to 133-MHz, and offers a bandwidth up to 2.1-Gbytes/sec. ExtremeDSP's DSP functions are implemented with soft silicon IP. Virtex-II, at 0.15-microns, has fully distributed registers and RAM for finite-impulse-response (FIR) filters, up to 3.5-Mbits of embedded dual-port SRAM, and embedded 18 x 18 multipliers for MAC operations. For communication with other system components, Platform FPGAs will use a variety of very fast serial and parallel I/Os, with every I/O pin programmable. Among the newer I/O choices are PCI-X133 (system-synchronous parallel), and RapidIO, LDT, and SPI-4 (source-synchronous parallel).

Figure 4: Xilinx's CSoC uses the IBM CoreConnect on-chip bus to connect a PowerPC 405 core with soft and hard silicon cores, including DSP functions embedded in the chip's FPGA fabric.

Cypress MicroSystems, a spin-off of Cypress Semiconductor, has a new mixed-signal PSoC (Programmable System-on-Chip) product. Like Atmel, Cypress bases its CSoC on an 8-bit microcontroller core, but adds configurable 8-bit digital and analog blocks, along with SRAM and, a unique capability, flash memory. PSoC's flash-memory is enabled by a special process, SONOS, that permits fabrication of electrically erasable, programmable, non-volatile memories. Chip cores are connected through an 8-bit bus that's a modified version of a bus Cypress Semiconductor uses on USB products.

You personalize a digital PSoC block to obtain functions such as a counter, serial port, CRC generator, or pseudo-random number generator. PSoC blocks work together to increase function precision. For example, you make a 16-bit counter by combining two 8-bit counters. Analog PSoC blocks are programmable operational amplifier circuits you configure by setting registers and trimming the amplifiers. The analog configured blocks can be DACs, ADCs, analog drivers, or filters. The on-chip bus goes through peripheral blocks and to the chip's pins, giving the designer a broad (but not exhaustive) way to combine peripherals.

A unique PSoC application is in a two-way radio, where peripheral configurations and combinations change (by redefining state machines in the peripherals through register settings) depending on whether the radio is transmitting or receiving. Cypress also has pre-configured peripheral cores for commonly used functions. Down the road for the company are PSoC chips with different amounts of memory and peripheral combinations.

Figure 6: The CS2000 Reconfigurable Communications Processor family features an ARC processor core, PCI and memory controllers, and an ultra-fast, 32-bit, reconfigurable processing fabric that lets you reconfigure the chip within one clock cycle.

Of particular interest is the innovative reconfigurable processing fabric. The fabric comprises a reconfigurable tile-array that implements the chip's communications algorithms. Each tile has seven 32-bit reconfigurable datapath units (DPUs), two 16x24-bit multipliers, four blocks of local store memory (32 bits by 128 words), and a control-logic unit. There are three tiles per slice on the chip"CS2000 chips have 3, 6, or 12 tiles, corresponding to 1, 2, or 4 slices. Each chip has a set of distributed DMA controllers to help data flow into and out of the processing fabric. You can reconfigure the fabric within one clock cycle. Chameleon boasts some very impressive performance figures for the CS2000 family"24,000 MOPS, 3000 16-bit MMACS, and 50 channels of cdma2000 chip-rate processing.

Through internally developed tools or with relationships with third-party development- and design-software vendors, CSoC vendors offer design packages for developing chips and embedded software with their CSoC products. Tools for designing the hardware are reasonably comprehensive, as are embedded-software development tools, particularly if the CSoC vendor has partnered with an established development-software vendor. However, hardware/software co-design tools still leave a lot to be desired for full CSoC product development. In addition, developing a comprehensive DFT methodology for complex chips works reasonably well for hardware, but remains difficult for embedded software.

Another problem is the gap between what CSoC vendors announce and what is actually available. The products in this article have all been announced, but only some are currently in designers' hands. You can get the Altera Nios soft core now. Some CSoCs with embedded 8-bit processors"Triscend's E5 and Atmel's AT94K"are in production. Cypress' PSoCs will see samples and some production in the first quarter of 2001. However, most 32-bit processor-based CSoCs are further out.

Altera expects samples of its ARM-based XA family to be available in the first quarter of 2001 and MIPS-based XM samples in the second quarter of 2001. Xilinx won't have Virtex-II chips with embedded PowerPC 405 cores until mid-2001. QuickLogic's ESPs with embedded MIPS cores are due sometime in 2001 as well. You do have some 32-bit-core products available now. Triscend's ARM-based A7 is currently sampling, with production due in the first quarter of 2001. Samples of Chameleon's CS2000 are also available now and production is slated for the first quarter of 2001.