Design challenges in DRL

Distinct from FPGAs, DRL technologies tend to be space and power-efficient. In the right applications they can not only equal the performance of hard-wired circuitry, but can do so using similar die space, while adding the flexibility of a reprogrammable technology. Furthermore DRL technology is able to reconfigure faster than FPGAs - in nanoseconds rather than microseconds or milliseconds - and often in a single clock cycle.

Just as significantly DRL also holds the potential to reduce the risk and costs associated with product development. The flexible architecture of DRLs offers manufacturers the chance to alter high-performance chips after they had gone to market. This could be for the sake of bug fixes, or for quickly creating new product lines in a rapidly changing market.

All this sounds great. But if DRL holds such promise, where is it? Time and time again the market has seen DRL companies launch to great fanfare, only to sink into the mire a few years later. If DRL is such a great technology why do DRL companies keep failing? In a word, designability.

Over the years several companies have recognised the potential of DRL and attempted to integrate it into their product lines. But these efforts have been hampered by very lengthy design times.

The major problem with DRL design has been that it is relatively complicated to design using traditional languages such as Verilog or VHDL. This is due to those languages lacking structures to describe things like multiple-possible- connectivity and changes in connectivity over time. These concepts are central to the functioning of DRL solutions. It seems that there are, roughly speaking, three things that need to be tackled in order for the market to take advantage of the benefits of DRL.

Focus and realism

Firstly, companies need to be focussed and realistic in terms of the application area in which they’re going to utilise DRL. They should consider not only what part of a chip would actually benefit from DRL technology, but also what type of function is best-suited to DRL in order to extract the maximum functional ‘oomph’.

The most obvious application area for DRL is in digital signal processing (DSP). DRL is innately suited to parallel processing, which DSPs tend to need a lot of. DSPs also require a lot of duplicate resources in hard-wired chips, of which only a few are utlised at any given time. With a DRL design the specific resources required can be laid down clock-cycle-by-clock-cycle, leading to a big saving in silicon area.

DRL DSPs can avoid the resource-wastage associated with traditional DSPs by defining exactly what they need on each clock cycle.