Design Article
FPGA compilation on-site or in the cloud
Rick Kuhlman, National Instruments
8/9/2010 3:10 AM EDT
It is no secret that field-programmable gate arrays (FPGAs) are getting bigger and more complex all the time. The fabrication process creates smaller transistors and makes more dense chips packing more digital processing per nanometer. Engineers love to see advancement because it means they can do more with modern silicon, and many times NI LabVIEW FPGA Module technology helps by abstracting the complexity to a higher level so that engineers can more smoothly take advantage of these improvements. Unfortunately, there is one issue with FPGAs that continues to be a time sink and only gets worse with denser FPGAs: compilation time.
FPGAs are getting harder (not easier) to compile
The FPGA compiler is not one big monolithic algorithm. Instead, it is a collection of big complex algorithms. The computational challenge is taking your design through a flow that generates an optimized layout on a chip with millions of processing elements that you can configure in any way. The compiler uses synthesis to create a system of logical connections between processing elements. It then maps, places, and routes executing an iterative process to find the best solution to hook everything up on the physical chip while attempting to meet constraints set by the user.
As you can imagine, the mathematics behind finding a globally optimized solution to a problem that has infinite possibilities is, in the words of my electronics professor, Dr. Blalock, “nontrivial.” Hence, FPGA compilation can take hours, and only gets worse with higher-density silicon. The best thing you can do to improve compilation time is offload your compile to a separate high-end dedicated machine with lots of RAM and a good processor.
NI has revamped the LabVIEW FPGA compile server to make it easy to do this within your own company or even target those long compilations to a high-end computer in the “cloud.”
LabVIEW FPGA compile server overview
In LabVIEW 2010, NI spent significant development effort to revamp many parts of the LabVIEW FPGA compile server. This server handles your compilation once LabVIEW has completed the 'Generating Intermediate Files' step. The communication lines between the development environment and the LabVIEW FPGA compile server have all been converted to robust Web services, which has drastically increased the reliability of the server communication. It also serves to further decouple the compilation process from the development environment to allow easier offloading to compilation machines other than the local host (development computer).
While you could offload your compiles to another machine in previous versions of LabVIEW, the TCP peer-to-peer constant connection was not fault-tolerant to various issues like a development computer restart. It could also lose connection, in some cases, when you chose to continue working in LabVIEW during the compilation. The new compile server solves many of these issues and offers new features looking forward.
In addition to a communication revamp, which is essentially under the hood, LabVIEW 2010 features an updated user interface to the compile server from the development computer. It incorporates queuing, progress indication, and presynthesis compile estimates, which can show estimated resource usage for your design within a minute of starting the compilation.
FPGAs are getting harder (not easier) to compile
The FPGA compiler is not one big monolithic algorithm. Instead, it is a collection of big complex algorithms. The computational challenge is taking your design through a flow that generates an optimized layout on a chip with millions of processing elements that you can configure in any way. The compiler uses synthesis to create a system of logical connections between processing elements. It then maps, places, and routes executing an iterative process to find the best solution to hook everything up on the physical chip while attempting to meet constraints set by the user.
As you can imagine, the mathematics behind finding a globally optimized solution to a problem that has infinite possibilities is, in the words of my electronics professor, Dr. Blalock, “nontrivial.” Hence, FPGA compilation can take hours, and only gets worse with higher-density silicon. The best thing you can do to improve compilation time is offload your compile to a separate high-end dedicated machine with lots of RAM and a good processor.
NI has revamped the LabVIEW FPGA compile server to make it easy to do this within your own company or even target those long compilations to a high-end computer in the “cloud.”
LabVIEW FPGA compile server overview
In LabVIEW 2010, NI spent significant development effort to revamp many parts of the LabVIEW FPGA compile server. This server handles your compilation once LabVIEW has completed the 'Generating Intermediate Files' step. The communication lines between the development environment and the LabVIEW FPGA compile server have all been converted to robust Web services, which has drastically increased the reliability of the server communication. It also serves to further decouple the compilation process from the development environment to allow easier offloading to compilation machines other than the local host (development computer).
While you could offload your compiles to another machine in previous versions of LabVIEW, the TCP peer-to-peer constant connection was not fault-tolerant to various issues like a development computer restart. It could also lose connection, in some cases, when you chose to continue working in LabVIEW during the compilation. The new compile server solves many of these issues and offers new features looking forward.
In addition to a communication revamp, which is essentially under the hood, LabVIEW 2010 features an updated user interface to the compile server from the development computer. It incorporates queuing, progress indication, and presynthesis compile estimates, which can show estimated resource usage for your design within a minute of starting the compilation.
Fig 1: The new compilation status window incorporates the earlier compile estimates, queues, and more information about the compilation.
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anky
8/12/2010 3:36 AM EDT
I have one question about this. What if user don't trust the cloud provider and is not willing to give away his design on the cloud for the compilation as he might think his multi-million next generation chip might get in the hands of the competitor. I mean he wants to use the cloud service but without revealing his actual design.
Some think similar to homomorphic encryption scheme which allows computation on the encrypted data itself, and user doesn't need to provide his encryption Key.
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anky
8/12/2010 3:38 AM EDT
Sorry, i mean decryption key in last line
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mxyzplk
8/12/2010 12:41 PM EDT
@anky, that's a good idea - homomorphic encryption is a potentially interesting approach, though a very new field.
I do want to note a couple things about the security of the FPGA Compile Cloud offering that people who are concerned about security might find interesting - all traffic to and from our servers is done via HTTPS, all access to those servers is also restricted using secure certificates, and all your files are deleted off the server as soon as you retrieve them post compilation. All end user access to the service is securely authenticated and only you can access your files. We have a CISSP-certified security engineer on staff conducting scans and audits to ensure the safety of the service.
Now, you correctly point out the one gap in all this, which is that you still have to trust NI to comply with its privacy policy regarding your content. Homomorphic encryption may be one long term approach to that. In the meantime, if the above security safeguards aren't enough for your organization, we do have a product where you can set up your own internal compile farm on your company's premises. Then you don't have to trust anyone (except all the people at your company) but do have to manage the hardware yourself.
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anky
8/12/2010 12:50 PM EDT
Homomorphic schemes are still under development, i can understand this would ultimately be a long term goal. Anyways thanks for the insight !
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Dr DSP
8/12/2010 6:23 PM EDT
There is a downside to making it easy to spawn lots of design processes. I'm sure some people have run into this- someone struggles to get timing closure and spins up a bunch of designs with different constraints or 'seeds' in the hope of finding one that works. They go home to get some sleep and the farm gets stuck with a bunch of, probably unneeded, designs slowing things down for everyone else. If the managemnt system can't limit requests or at least flag these types of things the 'shared' resource becomes worthless (just like the story of the goat farmer using the commons and soon there is no grass left for anyone else).
Is there a feature to address this?
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mxyzplk
8/13/2010 7:03 PM EDT
Do you mean in the cloud offering or the in-house farm offering?
And how would you want a feature like this to work? As this is the first release of the farm, we're very interested in feedback on how it might be made easier to manage in your environment.
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GERALD.SHAPIRO
8/17/2010 3:40 PM EDT
One issue unstated is software revision control. Once you start debugging an FPGA design, you don't want any software updates because they might change the way a bug manifests. And once all the bugs are removed, you don't want any software updates because they might introduce a bug or two.
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ChakC
9/5/2010 9:22 AM EDT
I think it is a great idea to use the cloud for the FPGA compilation which could take many hours. We just need to check-in the design into the compilation queue on the cloud, the key issue would be security (recall Anky), and we need to avoid those Trojan ICs.
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