A/D Converter → FPGA → D/A Converter: The JESD204/A/B Standard – “Where the rubber meets the road”

Introduction
In the real world, signals are continuous (analog) in nature. However, the vast majority of today’s signal processing is performed in the discrete (digital) domain using sophisticated digital signal processing (DSP) algorithms. Thus, analog-to-digital (A/D) converters are used to take real-world analog signals from sensors and transform this data into its digital equivalent. Similarly, digital-to-analog (D/A) converters may be used to take digital signals and transform them into their analog counterparts.

A variety of different integrated circuits may be used to perform DSP. One group of devices that are seeing exponential growth in this arena is that of field-programmable gate arrays (FPGAs). These devices are of interest for a number of reasons, including the fact that they can be reconfigured to perform different tasks and they can implement DSP algorithms in a massively parallel fashion.

As analog sampling rates and resolutions increase, there is a corresponding increase in the amount of digital data that has to be transported between the A/D and D/A converters and the FPGAs that are used to perform the DSP. The solution is the JEDEC JESD204/A/B high-speed serial interconnect standard.

In the not-so-distant past, analog and digital hardware design engineers had little understanding of each other’s domains. This is no longer realistic. Achieving success in a highly competitive market with shrinking product design cycles and tightening time-to-market requirements requires the analog engineers to have a fundamental understanding FPGAs, the digital engineers to have a fundamental understanding of A/D and D/A techniques, and both groups to have an understanding of the way in which signals are transported back and forth between the two domains.

This paper presents a series of 101-type* topics introducing the concepts of A/D and D/A converters for the digital engineers and FPGAs for the analog engineers; also introduced for both groups are high-speed serial interconnect in general and the JEDEC JESD204/A/B high-speed serial interconnect standard in particular.

*It used to be common for colleges in America to give their various courses numbers: the 100-series for the first year, the 200-series for the second, the 300-series for the third, and so forth. The -01 course would be the simplest course or the foundation module that everybody had to take, so "Something 101" refers to a basic introduction.

A/D and D/A Conversion 101 (Introducing Analog to the Digital Guys)
In the early days of electronics, systems were predominantly analog in nature. This was due to a variety of reasons, including the fact that any desired signal processing, such as amplification, filtering, or smoothing, was typically simple in the scheme of things. Other considerations were that digital functions had relatively low performance, were relatively expensive, and – to a large extent – were not well understood.

Over time, however, it became possible to create millions (now billions) of transistors on a single integrated circuit. Also, the complexity and quantity of signal processing that was required grew beyond the capabilities of analog signal processing (ASP), while digital signal processing (DSP) algorithms grew in processing power and sophistication. Now, DSP is ubiquitous, appearing in just about every electronic product, from digital cameras, medical imaging systems, from smartphones to tablet computers, from MP3 players to radar, from robotic vision to motion and motor control systems… the list goes on. A typical scenario using an FPGA to perform the DSP is illustrated in Figure 1.


In this simple example, we commence on the left-hand side of the image with a signal in the analog domain. This signal is passed through an A/D converter**, which translates it into a digital equivalent. We can now process this data to our heart’s content using DSP algorithms implemented in an FPGA. Finally, we take the output from the FPGA, pass it through a D/A converter, and return the result to the real-world in which we live.

**A/D and D/A converters are often referred to as ADCs and DACs, respectively.

Let’s consider the A/D portion of this in a little more detail (the D/A is essentially the counterpart to this process). A transducer is a device that converts input energy of one form into output energy of another. Analog effects can manifest themselves in a variety of different ways such as heat and pressure. In order to be processed by a digital system, the analog quantity must be detected and converted into a suitable form by means of an appropriate transducer called a sensor. For example, a microphone is a sensor that detects sound and converts it into a corresponding voltage or current. A high-level view of the A/D conversion process can be represented as shown in Figure 2.


The output from the sensor typically undergoes some form of signal processing such as filtering and amplification before being passed to the A/D converter. This signal processing is generically referred to as conditioning. The A/D converter accepts the conditioned analog voltage and converts it into a series of equivalent digital values by sampling and quantization as illustrated in Figure 3.


The sampling usually occurs at regular time intervals and is triggered by the digital part of the system. The complete range of values that the analog signal can assume is divided into a set of discrete bands or quanta. At each sample time, the A/D converter determines which band the analog signal falls into (this is the “quantization” part of the process) and outputs the equivalent binary code for that band.

The main factor governing the accuracy of the conversion is the number of bands used. For example, a 3-bit code can represent only eight bands, each encompassing 12.5% of the analog signal’s range. By comparison, a 10-bit code can represent 1,024 bands, each encompassing approximately 0.098% of the signal’s range; a 12-bit code can represent 4,096 bands, each encompassing approximately 0.024% of the signal’s range; and a 14-bit code can represent 16,384 bands, each encompassing approximately 0.006% of the signal’s range. This means that we have a classical engineering trade-off. In the case of a music CD, for example, we want the best sound we can get, but the more bits we use to represent each sample, the more data*** we have to store and the more processing we have to perform. This also leads us to the concept of quantization noise or quantization error, which refers to the difference between the original real-world analog signal and the quantized digital value caused by rounding (or truncating) the analog signal to the nearest digital quanta.

***The term “data” is the plural of the Latin datum, meaning “something given.” The plural usage is still common, especially amongst scientists, so it’s not unusual to see expressions like “These data are...” However, it is becoming increasingly common to use “data” to refer to a singular group entity such as information; thus, an expression like “This data is...” would also be acceptable to a modern audience.

FPGAs 101 (Introducing FPGAs to the analog guys)
Around the beginning of the 1980s, it became apparent that there was a “gap” in the digital integrated circuit continuum. On the one hand there were programmable devices like simple PLDs (SPLDs) and complex PLDs (CPLDs), which were highly configurable and had fast design and modification times, but which couldn’t support large or complex functions.  At the other end of the spectrum were application-specific integrated circuits (ASICs), which can support extremely large and complex functions, but which are extremely expensive and time-consuming to design. Furthermore, once a design is implemented as an ASIC, it’s effectively “frozen in silicon”.

In order to address this gap, in 1984, a company called Xilinx introduced a new class of integrated circuit to the market; this new component was called a field programmable gate array (FPGA). One way to visualize an FPGA is as a large number of programmable logic block “islands” surrounded by a “sea” of programmable interconnect as illustrated in Figure 4.


Only a few logic blocks are shown here, but a modern FPGA device can contain hundreds of thousands of such blocks, each of which can be configured (programmed) to perform a specific function. Furthermore, the programmable interconnect can be configured to connect the inputs and outputs of the various logic blocks together as required.

The device will also include primary input/output (I/O) pins and pads (not shown here). These inputs and outputs can be configured to support a variety of I/O standards, to present different impedances to the outside world, and so forth.

The FPGA’s configuration cells can be implemented using a variety of technologies, including antifuse, Flash, and SRAM. Each technology has its own advantages and disadvantages, but the most sophisticated FPGAs are SRAM-based, because these devices can be implemented using standard CMOS manufacturing techniques at the latest-and-greatest integrated circuit process node. Also, SRAM-based FPGAs can be programmed and re-programmed on-the-fly while resident on the circuit board.

It should be noted that the FPGA architecture illustrated in Figure 4 is very simplistic. A more realistic architecture is reflected in Figure 5. In addition to hundreds of thousands of programmable logic blocks, which can be used to represent the equivalent of tens of millions of ASIC logic gates, a high-end FPGA can contain a variety of more complex functional blocks, including thousands of special DSP blocks, megabytes of memory, and – of particular interest to us here – large numbers of serializer/deserializer (SerDes or SERDES) blocks, which are used to implement high-speed serial communications protocols.



High-Speed Serial Communication 101
The traditional way to move large amounts of data between two (or more) devices on the same circuit board is to use a bus, which refers to a collection of signals that carry similar data and perform a common function.

Early microprocessor-based systems circa 1975 used 8-bit busses to pass data around. As the need to push more data around and to move the data faster increased, busses grew to 16 bits in width, then 32 bits, then 64 bits, and so forth. The problem is that this consumes a lot of pins on each device and requires a lot of tracks to connect the devices together. Routing these tracks such that they are all the same length and impedance and so forth becomes increasingly painful as boards grow in complexity. Furthermore, it becomes increasingly difficult to manage signal integrity issues (such as susceptibility to noise and crosstalk effects) when you are dealing with large numbers of bus-based tracks.

For this reason, today’s high-end FPGAs include special hard-wired SERDES transceiver blocks. These high-speed serial interfaces use one pair of differential signals to receive (RX) data and another pair to transmit (TX) data as illustrated in Figure 6. Of course, some applications may require only the RX or TX portions of the block. Also, the reason for using differential pairs (which refers to a pair of tracks that always carry complementary logical levels) is that these signals are less susceptible to noise from an external source, such as radio interference or another signal switching in close proximity to these tracks.


One very important point to note is that the clock is embedded in the data signal. Thus, the receiver portion of a transceiver includes clock and data recovery (CDR) circuitry that keys off the rising and falling edges of the incoming signal and automatically derives a clock that is representative of the incoming data rate. This would not be a major feat if the incoming signal were toggling back and forth between logic 0 and logic 1 values, in which case the clock and the data would effectively be identical as illustrated in Figure 7(a).


Things get a little trickier when the signal becomes more complex as illustrated in Figure 7(b). If the incoming signal commenced with three 1s followed by three 0s, as shown in this example, we couldn’t fault the clock recovery function for making an initial “guess” that the clock frequency was only 1/3 of its true value. As more data (and more transitions) arrive, however, the clock recovery function will refine its assumptions until it has derived the correct frequency. Once the receiver has locked down the clock, it uses this information to sample the incoming data stream at the center point of each bit in order to determine whether that bit is a logic 0 or a logic 1.

One term that you often hear in conjunction with this topic is consecutive identical digits (CIDs), which refers to occurrences such as our three logic 1 values shown in Figure 7(b). In order to address this, the transceiver blocks have to include some form of encoding – such as the 8-bit/10-bit (abbreviated to 8b/10b or 8B/10B) standard – in which each 8-bit “chunk” of data is augmented by two extra bits to ensure that the system never sends more than five 0s or five 1s in a row. In addition to aiding in clock recovery, this standard ensures that the signal is always DC-balanced (that is, it has the same amount of energy above and below the median) over the course of 20 bits (two 10-bit “chunks”).

Two additional concepts that are applicable here are pre-emphasis and equalization. Signals traveling across a high-speed serial interface are severely distorted (attenuated) by the time they arrive at the receiver. This is because the circuit board and its tracks absorb a lot of the high frequency content of the signal leaving only the lower frequency (slower changing) portions of the signal.

One technique that may be used to mitigate this effect is pre-emphasis, in which the first 0 in a string of 0s and the first 1 in a string of 1s are given a bit of a “boost” with a slightly higher voltage (in this context, we will consider “string” to refer to one or more bits). In a way, we can think of this as applying our own distortion in the “opposite direction” to the distortion coming from the circuit board as illustrated in Figure 8.


Equalization is somewhat related to pre-emphasis, except that it takes place at the receiver end of the high-speed interface. Equalization refers to a special amplification stage that boosts higher frequencies more than lower ones. As for pre-emphasis, we can think of this as applying our own distortion in the “opposite direction” to any distortion coming from the circuit board.

The amounts of pre-emphasis and equalization to be applied are typically configurable so as to accommodate different circuit board environments. Depending on the particular design, it may be necessary to employ pre-emphasis, equalization, or a mixture of both.

JEDEC JESD204/A/B 101
The JEDEC Solid State Technology Association, formerly known as the Joint Electron Devices Engineering Council (JEDEC), is an independent semiconductor engineering trade organization and standardization body with over 300 members, including some of the world's largest computer companies.

JEDEC JESD204 is an industry standard that was specifically designed to facilitate the interconnection of D/A and A/D converters to digital ICs in general, and FPGAs in particular. The first revision, the JESD204 2006 specification, brought the advantages of SERDES-based high-speed serial interfaces to data converters, but it supported only a single lane with a single link with a maximum bandwidth of 3.125 Gbps as illustrated in Figure 9.


In 2008, the second revision of the standard was released, JESD204A, which added support for multiple data lanes and also lane synchronization as illustrated in Figure 10. Lane synchronization enables JESD204A to be used in quadrature (I/Q) sampling systems, where this technology underpins modern 3G, 3G+, and 4G broadband wireless communications.


Now, a third revision of the specification, JESD204B, has been published. JESD204B supports 8B/10B encoding, pre-emphasis, and equalization. JESD204B also introduces new enhancements, including a higher maximum lane rate (higher bandwidth), support for deterministic latency, and support for harmonic frame clocking as illustrated in Table 1.

Note: Table 1 was reproduced from the article An early look at the JEDEC JESD204B third-generation high-speed serial interface for data converters (published 8/11/2011) by Maury Wood of NXP Semiconductors, JEDEC JESD204B TG Chairman, with Maury's kind permission.

The maximum lane rate supported by JESD204B-complient interfaces is 12.5 Gbps, which is a significant increase over the 3.125 Gbps offered by earlier versions of the standard. The concepts of deterministic latency and harmonic frame clocking are beyond the scope of this introduction; suffice it to say that that the enhancements offered by JESD204B are anticipated to drive the adoption of this interface by data acquisition system engineers worldwide.

Where the rubber meets the road...
The idiom “Where the rubber meets the road” means "When one gets to the action" or "When things start to get serious." In the context of communication data between the analog and digital domains, the JESD204B standard truly is the point where the rubber meets the road.

JESD204B is going to facilitate the creation of next-generation electronic systems, but the successful adoption and implementation of this standard means that the analog and FPGA designers are going to have to start communicating with each other a lot more!

On the digital side of the fence, leading FPGA manufacturers like Xilinx (www.xilinx.com) and Altera (www.altera.com) have embraced JESD204B and created the appropriate IP to implement this functionality.

Similarly, global data converter leader Analog Devices (www.analog.com) has implemented JESD204B in its next-generation of data converters and are on the verge of announcing an array of JESD204B-compliant products and signal chains (www.analog.com/JESD204).

Today, immediate and obvious applications for JESD204B-compliant products are in communications, medical ultrasound, and radar. In the not-so-distant future, the benefits provided by the B-standard and its “plug-and-play” integration between high-speed data converters and FPGAs will create opportunities for a wide range of other data-crunching system designs that require high throughput combined with on-the-fly processing flexibility.

About the author
Clive “Max” Maxfield is six feet tall, outrageously handsome, English and proud of it. In addition to being a hero, trendsetter, and leader of fashion, he is widely regarded as an expert in all aspects of electronics (at least by his mother).

Max received his B.Sc. in Control Engineering in 1980 from Sheffield Hallam University, Sheffield, England. He began his career as a designer of central processing units (CPUs) for mainframe computers. Over the years, Max has designed everything from silicon chips to circuit boards, and from brainwave amplifiers to Steampunk “Display-O-Meters”. He has also been at the forefront of Electronic Design Automation (EDA) for more than 20 years.

Max is the author and/or co-author of a number of books, including Designus Maximus Unleashed (Banned in Alabama), Bebop To The Boolean Boogie (An Unconventional Guide to Electronics), EDA (Where Electronics Begins), FPGAs (Instant Access), and How Computers Do Math.

Max is also the editor of EE Times' Programmable Logic Designline and Microcontroller Designline Websites. He can be contacted at max@CliveMaxfield.com

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