All of the logic circuits remained functional through the test temperature range. However, the same was not true of the flash memory. During testing, we found that the on-board flash memory became unstable at -110°C. Starting at that temperature, it took couple of attempts to program the flash memory from JTAG. Nevertheless we were able to do so after two tries. In addition, the on-board flash memory became nonfunctional at -140°C. We weren’t able to program the flash from JTAG thereafter.
The internal 1.0V current increased significantly (384 mA) when we tried to configure the FPGA from nonfunctional flash memory. This result makes sense, since we are not sure what the state of FPGA I/Os would be once the FPGA is configured from nonfunctional flash memory. The 1.0V internal current became normal once the FPGA was configured through the JTAG port. Meanwhile, JTAG communication through IMPACT was functional throughout the test temperature range.
Additionally, ChipScope Pro was functional throughout the test temperature range and with it we were able to monitor the die temperature, 1.0V internal and 2.5V auxiliary voltage. They all tracked very closely with the external LabVIEW and temperature sensor measurements. This is important since it tells us that the Xilinx system monitor including the internal A/D was functional throughout the test.
At the end, we brought the temperature back to ambient, in increments, and left the unit under test to stabilize for 48 hours. In performing our end-to-end test, we were able to configure the Xilinx FPGA from JTAG only once. JTAG communication including the ChipScope Pro stopped thereafter, even though we were able to initialize the JTAG chain through IMPACT. We weren’t able to program the flash or configure the FPGA from either JTAG or flash memory. After removing the flash and rewiring the TDI/TDO chain, we were able to configure the FPGA thru the JTAG once again. This is important, since it shows that the FPGA wasn’t damaged.
It is important to note that the JTAG chain is serial. The TDO of the IMPACT is connected to TDI of the flash memory, and then the TDO of the flash memory is linked to the TDI of the Xilinx FPGA. This means that the flash memory is sitting between the IMPACT and the Xilinx FPGA.
Xilinx FPGA testing using commercial parts showed some promising results as far as reconfiguration at very low temperatures. Reconfiguration through the JTAG interface continued to work down to -150°C. However, due to what appears to be a failure of the flash memory chip at -130°C, we were not able to reconfigure the Virtex-5 chip from flash memory below that temperature.
Internal current steadily declined on the internal 1.0V as expected (and internal power consumption) and ended at 66 percent of where it was at room temperature. Basic circuits, ring oscillator, shift registers and PLL outputs continued to function normally with hardly any detectable changes.
About the author:
Bakhshi, Principal, B&A Engineering Systems Inc.
Bakhshi can be reached at email@example.com
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