Design Article
How partial dynamic reconfiguration helped make an FSK demodulator
Fabio Giovagnini and Antonio Di Marzo, SESM S.C.A.R.L.
10/2/2012 5:54 PM EDT
Editor's Note: This article is from the third quarter edition 2012 of the Xilinx Xcell Journal, and is reproduced here with the kind permission of Xilinx.
Partial dynamic reconfiguration is a radical new way to configure and reprogram an FPGA. Unlike the standard FPGA reconfiguration process, PDR allows you to change a small part of the device based on the needs of your design, while other parts are still running. There is no need to hold the device in reset while an external controller or internal piece of glue logic reloads a design onto it, the standard reconfiguration methodology. With PDR, critical parts of the design continue operating while a controller, either on or off the FPGA, loads a partial design into a reconfigurable module. The technique pays off in hardware resource optimization and a reduction in power consumption.
The PDR method has emerged as a topic for investigation in the context of the European Union research project pSHIELD. This project aims at pioneering techniques to build security, privacy and dependability (SPD) into embedded systems, rather than tacking them on as “add-on” functionalities. The idea behind pSHIELD is to take a first step toward SPD certification for future embedded systems. The leading concept is to demonstrate the composability of SPD technologies.
In such a context, we have identified PDR as a key technology to implement a secure, dependable and reconfigurable embedded system. Our investigation of this new technology involved implementing a project demonstrator—a reconfigurable frequency shift-keying (FSK) demodulator system—within the Xilinx PDR design flow.
Frequency shift-keying adaptable demodulator
The FSK adaptable demodulator is a proof of concept that we developed to demonstrate the pSHIELD SPD paradigm. In fact, it implements a simple system managing a data stream. Figure 1 shows the block diagram of the hardware implementation of the A-FSK demodulator SPD node.
Figure 1. Hardware implementation of the A-FSK demodulator SPD node.
One of the most common forms of digital modulation in the high-frequency radio spectrum, frequency shift keying has important applications in telephone circuits. This technology transmits data by shifting the frequency of a continuous carrier in a binary way. One frequency is designated as the “mark,” with frequency f0, and the other as “space,” with frequency f1. The mark is associated with the symbol one, the higher frequency, while the space is associated with the symbol zero, the lower frequency. In the example of the FSK signal seen in Table 1, the mark is at frequency 1,031 Hz and the space at 968 Hz.
Table 1. Mark and space in an example FSK signal.
After the FSK performs the demodulation, the signal and the carrier are multiplied together (or nco and multiplier, I2 and I1 blocks in Figure 2) and then low-pass filtered. This low-pass or loop (I3 block in Figure 2) filter discriminates the symbol mark from the space. The amplitude of the space symbol will be higher than that of the mark.
Figure 2. Block diagram of the FSK demodulator circuit.
The output of that loop filter goes to a 16-tap finite impulse response (FIR; I4 block in Figure 2) filter to perform digital low-pass filtering. The FIR filter is essentially an average filter, since its output is equal to the average value of its input over the last n-tap samples, where n is the number of taps used. This configuration needs 16 coefficients, but you can simplify the process by assuming all the coefficients are the same, 1/16. In reality, you can implement a 1/16 multiply by just performing a 4-bit right-shift operation.
The FSK adaptable demodulator is capable of adapting dynamically to a different frequency of the carrier Fc0 and Fc1. In a general communications schema, two modules are present: the modulator and the demodulator. An adaptable demodulator is able to switch automatically between two different carriers in order to match a carrier switch made by the modulator. The modulator might switch carriers for several reasons, including transmission errors, too much noise or the risk of intrusion on the current carrier.
The FSK adaptive demodulator has an additional built-in block named the carrier controller. This block continually checks the integrity of the transmitted signal by analyzing the consistency of received data. Based on that analysis, the carrier controller drives the reconfiguration condition.
The FSK adaptive demodulator can reconfigure itself in two distinct modes, each able to decode the signal modulated at the given carrier frequency Fc0 and Fc1. The process of configuration takes place in accordance with the partial dynamic reconfiguration methods. Figure 3 shows the general layout of the FSK adaptive demodulator. The carrier controller, which we implemented via software, runs on a PowerPC 440 as a single task and it performs a data integrity check. In the case of a communication error, the carrier controller will force a reconfiguration event, using the Internal Configuration Access Port (ICAP) software primitives.
We designed our FSK adaptive demodulator using the Xilinx developer board ML507. Equipped with RocketIO GTX transceivers, this embedded-system FPGA development board provides a feature-rich, general-purpose evaluation and development platform. It includes onboard memory and industry-standard connectivity interfaces to deliver a versatile development platform for embedded applications.
Next: PDR design flow
Partial dynamic reconfiguration is a radical new way to configure and reprogram an FPGA. Unlike the standard FPGA reconfiguration process, PDR allows you to change a small part of the device based on the needs of your design, while other parts are still running. There is no need to hold the device in reset while an external controller or internal piece of glue logic reloads a design onto it, the standard reconfiguration methodology. With PDR, critical parts of the design continue operating while a controller, either on or off the FPGA, loads a partial design into a reconfigurable module. The technique pays off in hardware resource optimization and a reduction in power consumption.
The PDR method has emerged as a topic for investigation in the context of the European Union research project pSHIELD. This project aims at pioneering techniques to build security, privacy and dependability (SPD) into embedded systems, rather than tacking them on as “add-on” functionalities. The idea behind pSHIELD is to take a first step toward SPD certification for future embedded systems. The leading concept is to demonstrate the composability of SPD technologies.
In such a context, we have identified PDR as a key technology to implement a secure, dependable and reconfigurable embedded system. Our investigation of this new technology involved implementing a project demonstrator—a reconfigurable frequency shift-keying (FSK) demodulator system—within the Xilinx PDR design flow.
Frequency shift-keying adaptable demodulator
The FSK adaptable demodulator is a proof of concept that we developed to demonstrate the pSHIELD SPD paradigm. In fact, it implements a simple system managing a data stream. Figure 1 shows the block diagram of the hardware implementation of the A-FSK demodulator SPD node.
Figure 1. Hardware implementation of the A-FSK demodulator SPD node.
One of the most common forms of digital modulation in the high-frequency radio spectrum, frequency shift keying has important applications in telephone circuits. This technology transmits data by shifting the frequency of a continuous carrier in a binary way. One frequency is designated as the “mark,” with frequency f0, and the other as “space,” with frequency f1. The mark is associated with the symbol one, the higher frequency, while the space is associated with the symbol zero, the lower frequency. In the example of the FSK signal seen in Table 1, the mark is at frequency 1,031 Hz and the space at 968 Hz.
Table 1. Mark and space in an example FSK signal.
After the FSK performs the demodulation, the signal and the carrier are multiplied together (or nco and multiplier, I2 and I1 blocks in Figure 2) and then low-pass filtered. This low-pass or loop (I3 block in Figure 2) filter discriminates the symbol mark from the space. The amplitude of the space symbol will be higher than that of the mark.
Figure 2. Block diagram of the FSK demodulator circuit.
The output of that loop filter goes to a 16-tap finite impulse response (FIR; I4 block in Figure 2) filter to perform digital low-pass filtering. The FIR filter is essentially an average filter, since its output is equal to the average value of its input over the last n-tap samples, where n is the number of taps used. This configuration needs 16 coefficients, but you can simplify the process by assuming all the coefficients are the same, 1/16. In reality, you can implement a 1/16 multiply by just performing a 4-bit right-shift operation.
The FSK adaptable demodulator is capable of adapting dynamically to a different frequency of the carrier Fc0 and Fc1. In a general communications schema, two modules are present: the modulator and the demodulator. An adaptable demodulator is able to switch automatically between two different carriers in order to match a carrier switch made by the modulator. The modulator might switch carriers for several reasons, including transmission errors, too much noise or the risk of intrusion on the current carrier.
The FSK adaptive demodulator has an additional built-in block named the carrier controller. This block continually checks the integrity of the transmitted signal by analyzing the consistency of received data. Based on that analysis, the carrier controller drives the reconfiguration condition.
The FSK adaptive demodulator can reconfigure itself in two distinct modes, each able to decode the signal modulated at the given carrier frequency Fc0 and Fc1. The process of configuration takes place in accordance with the partial dynamic reconfiguration methods. Figure 3 shows the general layout of the FSK adaptive demodulator. The carrier controller, which we implemented via software, runs on a PowerPC 440 as a single task and it performs a data integrity check. In the case of a communication error, the carrier controller will force a reconfiguration event, using the Internal Configuration Access Port (ICAP) software primitives.
Figure 3. Overview of the FSK adaptive demodulator design.
We designed our FSK adaptive demodulator using the Xilinx developer board ML507. Equipped with RocketIO GTX transceivers, this embedded-system FPGA development board provides a feature-rich, general-purpose evaluation and development platform. It includes onboard memory and industry-standard connectivity interfaces to deliver a versatile development platform for embedded applications.
Next: PDR design flow
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