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JESD204B vs. Serial LVDS I/F for wideband data converter apps
George Diniz, Analog Devices
11/6/2012 3:51 PM EST
LVDS overview
Low-voltage differential signaling (LVDS) is the traditional method of interfacing data converters with FPGAs or DSPs. LVDS was introduced in 1994 with the goal of providing higher bandwidth and lower power dissipation than the existing RS-422 and RS-485 differential transmission standards. LVDS was standardized with the publication of TIA/EIA-644 in 1995. The use of LVDS increased in the late 1990s and the standard was revised with the publication of TIA/EIA-644-A in 2001.
LVDS uses differential signals with low-voltage swings for high-speed data transmission. The transmitter typically drives ±3.5 mA with a polarity matching the logic level to be sent through a 100-ohm resistor, generating a ±350-mV voltage swing at the receiver. The always-on current is routed in different directions to generate logic ones and zeros. The always-on nature of LVDS helps eliminate simultaneous switching noise spikes and potential electromagnetic interference that sometimes occur when transistors are turned on and off in single-ended technologies. The differential nature of LVDS also provides considerable immunity to common-mode noise sources. The TIA/EIA-644-A standard recommends a maximum data rate of 655 Mbps, although it predicts a possible speed of over 1.9 Gbps for an ideal transmission medium.
Figure 3. Challenges in system design and
interconnect using parallel CMOS or LVDS.
The huge increase in the number and speed of data channels between FPGAs or DSPs and data converters, particularly in the applications described earlier has created several issues with the LVDS interface (See Figure 3). The bandwidth of a differential LVDS wire is limited to about 1.0 Gbps in the real world. In many current applications, this creates the need for a substantial number of high-bandwidth PCB interconnects, each of which is a potential failure point. The large number of traces also increases PCB complexity or overall form factor, which raises both design and manufacturing costs. In some applications, the data converter interface becomes the limiting factor in achieving the required system performance in bandwidth hungry applications.
JESD204B overview
The JESD204 data converter serial interface standard was created by the JEDEC Solid State Technology Association JC-16 Committee on Interface Technology with the goal of providing a higher speed serial interface for data converters to increase bandwidth and reduce the number of digital inputs and outputs between high-speed data converters and other devices. The standard builds on 8b/10b encoding technology developed by IBM that eliminates the need for a frame clock and a data clock, enabling single line pair communications at a much higher speed.
In 2006 JEDEC published the JESD204 specification for a single 3.125-Gbps data lane. The JESD204 interface is self-synchronous, so there is no need to calibrate the length of the PCB wire traces to avoid clock skew. JESD204 leverages the SerDes ports offered on many FPGAs to free up general-purpose I/O.
Figure 4. JESD204 with its high speed serial I/O capability
solves the system PCB complexity challenge.
JESD204A, published in 2008, adds support for multiple time-aligned data lanes and lane synchronization. This enhancement makes it possible to use higher bandwidth data converters and multiple synchronized data converter channels and is particularly important for wireless infrastructure transceivers used in cellular base stations. JESD204A also provides multi-device synchronization support which is useful for devices, such as medical imaging systems, that use large numbers of ADCs.
JESD204B, the third revision of the spec, increases the maximum lane rate to 12.5 Gbps. JESD204B also adds deterministic latency, which communicates synchronization status between the receiver and transmitter. Harmonic clocking, also introduced in JESD204B, makes it possible to derive a high-speed data converter clock from a lower-speed input clock with deterministic phasing.
Summary
The JESD204B industry serial interface standard reduces the number of digital inputs and outputs between high-speed data converters and FPGAs and other devices. Fewer interconnects simplifies layout and makes it possible to achieve a smaller form factor (see Figure 4). These advantages are important for a wide range of high-speed data converter applications such as wireless infrastructure transceivers, software defined radios, medical imaging systems, and radar and secure communications.
Analog Devices is an original participating member of the JESD204 standards committee and we have concurrently developed compliant data converter technology and tools along with a comprehensive product roadmap offering. By providing customers with products that combine our cutting edge data converter technology along with the JESD204A/B interface, we expect to enable customers to solve their system design problems, while taking advantage of this significant interfacing breakthrough.
About the author
George Diniz is a Product Line Manager in High Speed Digital to Analog Converters at Analog Devices in Greensboro, NC. He leads a team responsible for the development of JESD204B Rx and Tx interface cores, which are integrated into High Speed Analog to Digital and Digital to Analog converter products.
George has 25 years of experience in the semiconductor industry and has held various roles in design engineering and product line management. Before joining Analog Devices, George was a design engineer at IBM, where he was engaged in mixed-signal design of custom SRAM macros, PLL and DLL functions for PowerPC processors. He has an MSEE from North Carolina State University and a BEE from Manhattan College. For recreation, George enjoys outdoor activities, restoring automobiles and running.
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
Low-voltage differential signaling (LVDS) is the traditional method of interfacing data converters with FPGAs or DSPs. LVDS was introduced in 1994 with the goal of providing higher bandwidth and lower power dissipation than the existing RS-422 and RS-485 differential transmission standards. LVDS was standardized with the publication of TIA/EIA-644 in 1995. The use of LVDS increased in the late 1990s and the standard was revised with the publication of TIA/EIA-644-A in 2001.
LVDS uses differential signals with low-voltage swings for high-speed data transmission. The transmitter typically drives ±3.5 mA with a polarity matching the logic level to be sent through a 100-ohm resistor, generating a ±350-mV voltage swing at the receiver. The always-on current is routed in different directions to generate logic ones and zeros. The always-on nature of LVDS helps eliminate simultaneous switching noise spikes and potential electromagnetic interference that sometimes occur when transistors are turned on and off in single-ended technologies. The differential nature of LVDS also provides considerable immunity to common-mode noise sources. The TIA/EIA-644-A standard recommends a maximum data rate of 655 Mbps, although it predicts a possible speed of over 1.9 Gbps for an ideal transmission medium.
Figure 3. Challenges in system design and
interconnect using parallel CMOS or LVDS.
The huge increase in the number and speed of data channels between FPGAs or DSPs and data converters, particularly in the applications described earlier has created several issues with the LVDS interface (See Figure 3). The bandwidth of a differential LVDS wire is limited to about 1.0 Gbps in the real world. In many current applications, this creates the need for a substantial number of high-bandwidth PCB interconnects, each of which is a potential failure point. The large number of traces also increases PCB complexity or overall form factor, which raises both design and manufacturing costs. In some applications, the data converter interface becomes the limiting factor in achieving the required system performance in bandwidth hungry applications.
JESD204B overview
The JESD204 data converter serial interface standard was created by the JEDEC Solid State Technology Association JC-16 Committee on Interface Technology with the goal of providing a higher speed serial interface for data converters to increase bandwidth and reduce the number of digital inputs and outputs between high-speed data converters and other devices. The standard builds on 8b/10b encoding technology developed by IBM that eliminates the need for a frame clock and a data clock, enabling single line pair communications at a much higher speed.
In 2006 JEDEC published the JESD204 specification for a single 3.125-Gbps data lane. The JESD204 interface is self-synchronous, so there is no need to calibrate the length of the PCB wire traces to avoid clock skew. JESD204 leverages the SerDes ports offered on many FPGAs to free up general-purpose I/O.
Figure 4. JESD204 with its high speed serial I/O capability
solves the system PCB complexity challenge.
JESD204A, published in 2008, adds support for multiple time-aligned data lanes and lane synchronization. This enhancement makes it possible to use higher bandwidth data converters and multiple synchronized data converter channels and is particularly important for wireless infrastructure transceivers used in cellular base stations. JESD204A also provides multi-device synchronization support which is useful for devices, such as medical imaging systems, that use large numbers of ADCs.
JESD204B, the third revision of the spec, increases the maximum lane rate to 12.5 Gbps. JESD204B also adds deterministic latency, which communicates synchronization status between the receiver and transmitter. Harmonic clocking, also introduced in JESD204B, makes it possible to derive a high-speed data converter clock from a lower-speed input clock with deterministic phasing.
Summary
The JESD204B industry serial interface standard reduces the number of digital inputs and outputs between high-speed data converters and FPGAs and other devices. Fewer interconnects simplifies layout and makes it possible to achieve a smaller form factor (see Figure 4). These advantages are important for a wide range of high-speed data converter applications such as wireless infrastructure transceivers, software defined radios, medical imaging systems, and radar and secure communications.
Analog Devices is an original participating member of the JESD204 standards committee and we have concurrently developed compliant data converter technology and tools along with a comprehensive product roadmap offering. By providing customers with products that combine our cutting edge data converter technology along with the JESD204A/B interface, we expect to enable customers to solve their system design problems, while taking advantage of this significant interfacing breakthrough.
About the author
George Diniz is a Product Line Manager in High Speed Digital to Analog Converters at Analog Devices in Greensboro, NC. He leads a team responsible for the development of JESD204B Rx and Tx interface cores, which are integrated into High Speed Analog to Digital and Digital to Analog converter products.George has 25 years of experience in the semiconductor industry and has held various roles in design engineering and product line management. Before joining Analog Devices, George was a design engineer at IBM, where he was engaged in mixed-signal design of custom SRAM macros, PLL and DLL functions for PowerPC processors. He has an MSEE from North Carolina State University and a BEE from Manhattan College. For recreation, George enjoys outdoor activities, restoring automobiles and running.
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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