Design Article
Free Webinar: Best Design Practices for High-Capacity FPGA Devices
Clive Maxfield
1/4/2013 1:38 PM EST
Well, this is a "Cool Beans" day, because I just heard that the folks at Aldec are going to be hosting a free webinar on the topic of best design practices for high-capacity FPGA devices – and some of today's FPGAs are VERY high capacity indeed!
This webinar, which will be presented by Aldec Research Engineer Deep Shah, will take place on Thursday, 24 January, 2013. In fact, there will be two sessions – one for folks in the US and another for folks in Europe:
Even if these particular dates or times do not fit your schedule or time zone, the guys and gals at Aldec still invite you to go ahead and register for the event because – following the Webinar – all registrants will be emailed a link to view the recorded presentation at their convenience.
Abstract
With the latest FPGA technology advancements and release of high capacity devices such as Xilinx Virtex-7 and Altera Stratix-V, design teams face more challenges producing safe and clean HDL (RTL, FPGA) code. In this presentation, we will focus on the design techniques that will result in the code running most optimally on the large FPGA designs, and be free of timing and synchronization issues.
Agenda
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
This webinar, which will be presented by Aldec Research Engineer Deep Shah, will take place on Thursday, 24 January, 2013. In fact, there will be two sessions – one for folks in the US and another for folks in Europe:
US Session
Time: 11:00am-12:00pm PST
Register for the US Session
EU Session
Time: 3:00pm-4:00pm CET
Register for the European Session
Even if these particular dates or times do not fit your schedule or time zone, the guys and gals at Aldec still invite you to go ahead and register for the event because – following the Webinar – all registrants will be emailed a link to view the recorded presentation at their convenience.
Abstract
With the latest FPGA technology advancements and release of high capacity devices such as Xilinx Virtex-7 and Altera Stratix-V, design teams face more challenges producing safe and clean HDL (RTL, FPGA) code. In this presentation, we will focus on the design techniques that will result in the code running most optimally on the large FPGA designs, and be free of timing and synchronization issues.
Agenda
- Catching undesirable memory element inferences and improving simulation performance
- Avoiding combinational feedback loops that are hard to spot
- What can lead to RTL and post synthesis simulation mismatch
- Data synchronization considerations at the clock domain crossing boundaries
- Reducing area and avoiding redundant logic generation in your design
- Minimizing routing delays
- Building automatic RTL analysis into your design flow
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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