The Histogram Plot
A third useful measurement is the histogram plot. This plot shows the distribution of the measured periods between transition points in the data transmission. As with the eye diagram and bathtub plot measurements, the histogram plots are from measurements on a JESD204B 5.0 Gbps transmitter measured at the receiver after passing through a connecter and approximately 20 cm of transmission line. Figure 9 shows a histogram for a relatively good performing system at 5.0 Gbps. The histogram shows a mostly Gaussian type distribution with periods measured between 185 ps and 210 ps. The expected period for a 5.0 Gbps signal should be 200 ps which means the distribution is spread about -7.5% to +5% around its expected value.
Figure 9. 5.0 Gbps Histogram Plot
When an improper termination is introduced, as shown in Figure 10, the distribution becomes wider and now varies between 170 ps and 220 ps. This increases the percentage of variation from -15% to +10%, which is double that of the measurement shown in Figure 9. These plots show that mostly random jitter is present in the signal since they have a mostly Gaussian-like shape. However, since the shape is not exactly Gaussian in nature which indicates there is at least a small amount of deterministic jitter also.
Figure 10. 5.0 Gbps Histogram Plot – Improper Termination
The histogram presented in Figure 11 indicates the results of having an impedance discontinuity along the transmission line. The shape of the distribution is not Gaussian-like at all and has developed a small secondary hump. The mean value of the measured period is also skewed.
Figure 11. 5.0 Gbps Histogram Plot – Impedance Discontinuity
Unlike the plots in Figure 9 and Figure 10, the mean is no longer 200 ps, it has shifted to about 204 ps. The more bi-modal distribution indicates that there is more deterministic jitter in the system. This is due to the impedance discontinuity present on the transmission lines and the predictable impacts this has on the system. The range of values measured for the period is again increased, although not as much as in the case of the improper termination. In this case, the range is from 175 ps up to 215 ps, which is a range of approximately -12.5% to +7.5% of the expected period. The range isn't as large, but again, the distribution is more bi-modal in nature.
Several performance metrics can be used to evaluate the performance of the physical layer of a JESD204B transmitter. These include common mode voltage, differential peak-to-peak voltage, differential impedance, differential output return loss, common mode return loss, transmitter short circuit current, eye diagram mask, and jitter.
Three key performance metrics have been discussed that are used to evaluate the quality of the transmitted signal. The eye diagram, bathtub plot, and histogram plot are three important performance metrics that are used to evaluate the quality of the JESD204B link. System issues such as improper terminations and impedance discontinuities have significant impact on the performance of the physical layer. These impacts are evidenced by the degraded performance shown in the eye diagrams, bathtub plots, and histogram plots.
It is important to maintain good design practices to properly terminate the system and to avoid impedance discontinuities in the transmission media. These have appreciable negative effects on the data transmission and can result in a faulty data link between the JESD204B transmitter and receiver. Employing techniques to avoid these issues will help to ensure a properly working system.
About the author
JEDEC Standard JESD204B (July 2011). JEDEC Solid State Technology Association. www.jedec.org
Application Note 5989-5718EN: Using Clock Jitter Analysis to Reduce BER in Serial Data Applications. Agilent Technoloiges, December 2006.
Application Note 5988-9109EN: Measuring in Digital Systems. Agilent Technologies, January 2008.
Jonathan Harris is a product applications engineer in the high speed converter group at Analog Devices in Greensboro, NC. He has over 7 years of experience as an applications engineer supporting products in the RF industry.
Jonathan received his MSEE from Auburn University and his BSEE from UNC-Charlotte. In his spare time he enjoys mobile audio, nitro R/C, college football, and spending time with his two children. He can be reached via email at firstname.lastname@example.org
If you found this article to be of interest, visit Programmable Logic Designline
where – in addition to my Max's Cool Beans
blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here
to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).