The serial peripheral interface (SPI) bus is a synchronous serial data link operating in full-duplex mode. It is used to exchange data between a single master and one or multiple slaves. Its simple implementation uses only four signal lines for data and control (Figure 1):

Figure 1: Basic SPI Bus
(Click on image to enlarge)

While the pin names in Table 1 are taken from the SPI standard developed by Motorola, SPI port names for particular integrated circuits usually differ from those depicted in Figure 1.

Table 1: SPI pin name assignments
(Click on image to enlarge)

SPI data rates are commonly in the range of 1 to 70 MHz and byte lengths can range from 8- and 12-bits to multiples of these values.

Data transfers always consist of a data exchange. While the master is sending data to the slave, the slave sends data to the master. For this reason the master's internal shift registers and slave are set-up in a ring formation (Figure 2).

Figure 2: The two-shift registers form an inter-chip circular buffer
(Click on image to enlarge)

Prior to a data exchange, the master and slave load their internal shift registers with memory data. Upon a clock signal, the master clocks out its shift register MSB first via MOSI line. At the same time the slave reads the first bit from the master at SIMO, stores it into memory, and clocks out its MSB via SOMI. The master reads the slave's first bit at MISO and stores it into memory for later processing. The entire procedure continues until all bits are exchanged and the master idles the clock and disables the slave via /SS.

In addition to setting the clock frequency the master also configures the clock polarity and phase with respect to the data. These two options, known as CPOL and CPHA, allow for a 180° phase shift of the clock signal and a data delay of half a clock cycle. Figure 3 shows the corresponding timing diagram.

Figure 3: Timing diagram for clock polarity and phase
(Click on image to enlarge)

For CPOL = 0 the clock idles at logic zero:

• If CPHA = 0, data are read on the rising edge and change on the falling edge of SCK.
• If CPHA = 1, data are read on the falling edge and change on the rising edge of SCK.

• If CPHA = 0, data are read on the falling edge and change on the rising edge of SCK.
• If CPHA = 1, data are read on the rising edge and change on the falling edge of SCK.

Figure 4: Master communicating with independent slaves (left), and daisy-chained slaves (right)
(Click on image to enlarge)

Addressing slaves independently, the master must provide multiple slave-select signals. This configuration is often used in data acquisition systems where multiple analog-to-digital (ADCs) and digital-to-analog converters (DACs) must be accessed individually.

Daisy-chained slaves require the master to provide only one slave-select signal as this configuration demands all slaves to be enabled at the same time to ensure an uninterrupted flow of data through all shift registers within the chain. Typical applications are cascaded, multi-channel input serializers and output drivers in industrial I/O modules.

In the third part of Digital Interfaces for Signal Chain Basics, we'll discuss the I²C Bus.

About the Author


Thomas Kugelstadt is a Senior Systems Engineer at Texas Instruments, where he is responsible for defining new, high-performance analog products and developing complete system solutions that detect and condition low-level analog signals in industrial systems.
During his 20 years with TI, he has been assigned to various international application positions in Europe, Asia and the U.S. Thomas is a Graduate Engineer from the Frankfurt University of Applied Science. You can contact Thomas about this article at: scb@list.ti.com.

Previous installments of this series:

• SIGNAL CHAIN BASICS (Part 30): Protocol selection over IEEE 802.15.4 silicon, click here
• SIGNAL CHAIN BASICS (Part 29): Digital interfaces - Single-ended versus differential interfaces, click here
• SIGNAL CHAIN BASICS (Part 28): Building (Electrical) Bridges, click here
• SIGNAL CHAIN BASICS (Part 27): Control EMI resulting from board-level clock distribution, click here
• SIGNAL CHAIN BASICS (Part 26): How to close timing on High-Speed ADCs, click here
• SIGNAL CHAIN BASICS (Part 25): Designing the audio-signal chain for non-audio experts, Part 1, click here
• SIGNAL CHAIN BASICS (Part 24): Basic networking using the IEEE 802.15.4 PHY/MAC protocol, click here
• SIGNAL CHAIN BASICS (Part 23): EIA-485: Receiver equalization boosts networking performance, click here
• SIGNAL CHAIN BASICS (Part 22): Phantom microphone power--the ghost in the machine, click here
• SIGNAL CHAIN BASICS (Part 21): Understand and configure analog and digital grounds, click here
• SIGNAL CHAIN BASICS (Part 20): Understand the basics of op amps and speed, click here
• SIGNAL CHAIN BASICS (Part 19): Exploring and understanding linear voltage regulators, click here
• SIGNAL CHAIN BASICS (Part 18): The op amp as integrator, click here
• SIGNAL CHAIN BASICS (Part 17): Hysteresis--Understanding more about the analog voltage comparator, click here
• SIGNAL CHAIN BASICS (Part 16): Understanding the analog voltage comparator, click here
• SIGNAL CHAIN BASICS (Part 15): Analog/digital converter--dynamic parameters, click here
• SIGNAL CHAIN BASICS (Part 14): Analog/digital converter--static parameters, click here
• SIGNAL CHAIN BASICS (Part 13): Putting the Bode plot to use, click here
• SIGNAL CHAIN BASICS (Part 12): The Bode plot, an essential ac-parameter display tool, click here
• SIGNAL CHAIN BASICS (Part 11): Introducing voltage- and power-conditioning circuits, click here
• SIGNAL CHAIN BASICS (Part 10): Exploring the Delta-Sigma Converter, click here
• SIGNAL CHAIN BASICS (Part 9): SAR Converter Operation Explored, click here
• SIGNAL CHAIN BASICS (Part 8): Flash- and Pipeline-Converter Operation Explored, click here
• SIGNAL CHAIN BASICS (Part 7): Op Amp Performance Specification--Bias Current, click here
• SIGNAL CHAIN BASICS (Part 6): Op Amp Input Voltage Offset, click here
• SIGNAL CHAIN BASICS (Part 5): Introduction to the Instrumentation Amplifier, click here
• SIGNAL CHAIN BASICS (Part 4): Introduction to analog/digital converter (ADC) types, click here
• SIGNAL CHAIN BASICS (Part 3): Analog and the digital world, click here
• SIGNAL CHAIN BASICS (Part 2): Op Amp--Basic operations, click here
• SIGNAL CHAIN BASICS: Operational Amplifier--The Basic Building Block, click here