Today's video-capture systems make extensive use of the conventional 32-bit PCI interconnect, since low-cost PC platforms with PCI video cards enable system designers to create powerful systems using off-the-shelf building blocks. This not only lowers cost, but also enables designers to reduce the time to market, and lower the risks associated with proprietary architectures. But like so many other designs based on conventional PCI, video-capture systems are migrating to the newer and far more powerful PCI Express (PCIe) interconnect standard to help achieve lower cost per channel and higher bandwidth on each card's I/O segment. This bandwidth increase is necessary to accommodate the increased number of video channels, to allow increased image resolution, and to add audio to the streams from each channel as well.

This market dynamic is driving single-channel video cards to be replaced by multi-channel designs. Dual, quad, octal and even higher video channel count solutions are hitting the market. The deployment of several channels of video capture on a single board helps to increase the density of the video processing, lowering cost and reducing the space required for surveillance systems. This in turn increases the bandwidth required of the data stream and can result in a reduction in resolution when there is insufficient bandwidth on the I/O channel. PCIe brings the potential for significantly wider I/O bandwidth -- up to 32 times that of PCI. This, along with the move toward standardization of PCIe on lower-cost PC platforms, is driving the replacement of PCI and other I/O standards with PCIe.

This article explains how to increase the video capture system channel density through PCI and PCIe bridges and switches. Several examples of increasing channel count are used to illustrate:

1 - Using a synchronous PCIe-to-PCI (P2P) bridge to migrate a design from one channel to four

2 - Migrating a four-channel design into eight channels using a P2P bridge with enhanced bus arbitration

3 - Migrating a PCI-based design into PCIe by replacing a PCI-to-PCI bridge with a P2P bridge in forward mode

4 - Connecting an FPGA-based video encoder to a PCIe link via a local-bus-to-PCIe bridge

5 - Developing a 16-channel DVR card using quad-PCI capture chips

6 - Developing a 16-channel capture card using a PCIe switch

Next: Combining four PCI-based video capture processors on a single card using a P-P Bridge
Combining four PCI-based video capture processors on a single card using a P-P Bridge

Figure 1 illustrates a four-channel video capture add-in card that uses a 32-bit PCI interface to connect into a desktop system board. The video capture is performed with four Conexant Bt878 video processors, connecting to the 32-bit PCI bus. All four Bt878's are connected onto the secondary bus of a PLX PCI 6140 PCI-to-PCI bridge. (This bridge was designed to support up to four PCI devices on the secondary bus at 33MHz and perform load expansion from the system board PCI slot.)

The 240 x 480 resolution for each camera requires approximately 20 MB/s throughput for each video stream. Higher resolution images can be processed in this system only by reducing the number of channels.


Figure 1: Four-channel PCI-based video-capture card

Upgrading to eight channels requires a better Bridge
Figure 2 features eight of the same video chips on the secondary bus of a different P2P bridge, which includes a more robust arbiter. The bridge includes support for nine masters on the PCI secondary bus. This allows the connection of the eight video capture chips on a single card. Having eight devices on the secondary bus can cause congestion and produce artifacts in the video stream due to the bandwidth limitations of a single 32-bit PCI segment. This is solved by over-clocking the secondary bus to 50MHz.


Figure 2: Video-capture card upgraded to eight channels

Next: Upgrading to PCIe connectivity, using FPGA and local bus to PCIe Bridge
Upgrading to PCIe connectivity
Figure 3 illustrates the same video-capture system upgraded to include PCIe connectivity. PCIe connectivity is becoming increasingly more important, as more low cost systems are replacing PCI slots with PCIe slots. To get PCIe connectivity, the P2P bridge is replaced with a PCIe-to-PCI bridge. In addition, a complex programmable logic device (CPLD) is included to provide arbitration for eight PCI masters on the secondary bus of that PCIe bridge. This external arbiter is required because the PCIe-to-PCI bridge was designed to support only four PCI masters on the secondary bus. A photo of the 8-channel DVR card is shown in Figure 3.


Figure 3: Video-capture card upgraded to eight channels and PCIe

A more intuitive approach would be to place the PCIe bridge in front of the PCI bridge to solve the need for the CPLD arbiter. However, inserting an external arbiter on the PCI bus is less expensive and more efficient, in terms of latency timing and cost.

The standard PCI control lines are fed to the arbiter, but not the address and data lines. The arbiter samples the control signals to perform eight-channel arbitration.

The arbiter code is implemented utilizing approximately 500 gates, which is about 40 percent of an EPM3064A-10 CPLD. That CPLD has 64 logic cells (or about 1250 gates), and fits into a 44-pin PQFP 12mm x 12mm package. (The code can be downloaded from PLX at PLX.com. The connections for the arbiter are detailed in Figure 4.)


Figure 4: Connecting the arbiter CPLD

Next: Customized video capture using FPGA and local bus to PCIe Bridge, wider I/O link for higher resolution, 16-channel DVR card with MPEG4
Customized video capture using FPGA and local bus to PCIe Bridge
Many video capture cards utilize FPGA's to implement proprietary encoding and compression schemes, rather than use standard off-the-shelf video processors. Because these FPGA's typically do not include a standard PCI or PCIe I/O cell, a local-bus-to-PCIe bridge is required to connect to a standard I/O port such as PCIe (shown in Figure 4). One such bridge, the PLX PEX 8311, provides a 32-bit local bus and a x1 PCIe link and its on-board DMA engines can be used to provide higher bandwidth video throughput. This bandwidth may be used for more video channels and/or higher resolution video images.

Figure 5: FPGA-based Video Capture

Using a wider I/O link to allow higher resolution and more channel density
Increased image resolution will demand more from the I/O link. Video capture systems often have to reduce the resolution settings on the capture system to reduce or eliminate various image artifacts -- lines, for example -- which occur when the system bandwidth is exceeded. These artifacts occur due to processor overloading, lack of memory and I/O bandwidth constraints. This is where the migration to PCIe really pays off.

PCIe has scalable bandwidth, based on the number of lanes deployed in the link. Figure 6 shows the throughput associated with various PCIe link widths (x1 through x32) and compares it with equivalent PCI bus types. In column one of this chart, the effective maximum bandwidth of a x1 PCIe link is equal to the bandwidth of a 32-bit 66MHz bus segment (250MB/s). This bandwidth is sufficient for up to eight channels of uncompressed low-resolution video (240 x 480).


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Figure 6: PCIe Performance Compared with PCI

More bandwidth can be achieved in the I/O link by moving from a x1 PCIe link to a x4 PCIe link. As can be seen in the chart in Figure 6, a x4 link will have up to 4x the bandwidth of the x1 link, or up to 1GB/s. In practice, the 1GB/s is difficult to achieve, especially if bridges are inserted in the I/O path. The actual max bandwidth is more likely to be in the 800MB/s range, and this is highly dependent on the packet sizes and the length of the PCIe payload. For longer payloads, the overhead percentage associated with bridge latency and protocol translation is reduced, allowing higher throughput.

Next: 16-channel DVR card with MPEG4
16-channel DVR card supports 320 x 240 resolution with MPEG4
Using quad-video processors will increase the channel density, as shown in Figure 7.

The Techwell processors generate video streams, which are translated into PCI via an FPGA, and includes a standard 32-bit PCI bus interface. This DVR card can support up to 480 frames per second in NTSC format.


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Figure 7: Quad PCI Video Capture Chips PCIe Bridge

Increase bandwidth and channel density with PCIe Native Video Decoders and PCIe Switch
Figure 8 shows a PCIe implementation that utilizes a x4 upstream PCIe port to bring a higher bandwidth to the system to allow for processing more channels of video. The PCIe-native video processors take four camera channels and convert them to a single x1 PCIe stream. These four streams are aggregated into the PCIe switch. In this example, the PLX PEX 8508 switch is used, providing an eight-lane, five-port switch configured to aggregate four downstream x1 ports into a single x4 upstream port. This configuration reduces the latency associated with the previously shown versions, which use a PCI bus and a bridge to get PCIe connectivity.


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Figure 8: Using PCIe switches to get high resolution and high channel count

Summary
PCIe is beginning to be deployed in virtually every electronics application market, including video capture for surveillance and other uses such as medical imaging and broadcast editing. Existing solutions with PCI bridges will eventually give way to higher-performance solutions using PCIe-native video decoders and PCIe switches. As this available I/O bandwidth increases, system designers can expect to see commensurate improvements in DVR resolution and channel density.

About the author
Steve Moore is senior product marketing manager at PLX Technology, Sunnyvale, Calif. (plxtech.com). He holds a BSEE from the University of California, Berkeley, and has written articles for several industry publications. He can be reached at smoore@plxtech.com.