Design Article

CEO interview: with John Daane of Altera

12/29/2008 8:10 AM EST

Despite economic difficulties across the chip industry, FPGA makers didn't have it so bad in 2008. Altera Corp. announced increases in sales and net income for Q3 2008 over Q3 2007. John Daane, president, CEO and chairman of Altera, asserts that market slowdowns can be growth opportunities.

How did Altera achieve growth in Q3 08 despite general market slowdown?

John Daane: Altera remains committed to its fundamental themes of growth, efficiency and shareholder value, and we are pleased to have achieved all three goals for a second consecutive quarter. Our 65-nm devices — Cyclone III FPGAs and Stratix III FPGAs — had another strong growth quarter, with sales once again more than doubling sequentially.

Market slowdowns present an opportunity to accelerate the replacement of ASICs and ASSPs over the long term. System companies tighten budgets and cancel ASIC designs, and semiconductor companies rationalize their product portfolios and eliminate ASSP projects. Nevertheless, system differentiation is still required, and in the absence of ASICs and ASSPs, PLDs become the product of choice. It is here that our efforts to design innovative new software and silicon products pay off for our long-term growth prospects.

How has Altera performed so far this year?

JD: We are very pleased with our progress to date. Our new products are now 46 percent of our revenue, and sales of these devices have grown 52 percent year over year as we continue to replace ASICs and ASSPs.

In terms of market segments, we have seen the communications segment grow 24 percent year over year across 2G and 3G standards. We have also seen 25 percent year-over-year growth in the industrial segment, led by gains in the military, automotive and broad industrial markets.

Please tell us about the 40-nm Stratix IV FPGAs.

JD: Our Stratix IV devices are the industry's first 40-nm FPGAs and incorporate a unique architecture combining low-power consumption with high performance, high density and high-speed transceivers. To date, Stratix IV FPGAs have achieved record design engagements with nearly 600 customers in our early adopter program. This is more than twice the number of customers as any previous program. Customers use our Quartus II design software to design Stratix IV FPGAs into applications across all of Altera's market segments. We expect the first shipments of the Stratix IV devices by the end of this year. We have gained share in the FPGA market in each of the last six years with products noted for their architectural innovation. With the Stratix IV family, we offer customers benefits that are even more attractive based on a combination of both architectural and process-node leadership. As development costs for competing ASICs climb and engineers are forced to use older process technology, the economics and performance of leading-edge programmable logic become significantly more attractive. By moving quickly to the 40-nm node, Altera has placed the company in a strong position to compete for designs that were once the exclusive domain of ASIC-based solutions.

What about your multi-core devices?

JD: Because our Nios II processor uses a soft core, all of our FPGAs and HardCopy ASICs have the capability to be multi-core devices. The programmability of our FPGAs is a big advantage for designers considering a multi-core device because it allows them to design a device that fits their exact performance and power needs.

We simplify the task of multi-core designs through our Quartus II design software and SOPC Builder tool. This tool eliminates the manual system-integration tasks of IP blocks in an FPGA design. Designers can select functions from the Altera or third-party IP core libraries to include in their FPGA. SOPC Builder automatically generates interconnect logic and creates a test bench to verify functionality, thereby saving valuable design time.

In addition, because FPGAs have inherent parallelism, our devices compete well versus other multi-core architectures even without using Nios II processors.


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