Analysis: TI's three-core, 65-nm DSP

In December Texas Instruments announced the TCI6487 multi-core baseband processor. The device will be manufactured in a 65 nm process and is intended mainly for GSM, TD-SCDMA and WiMAX basestation applications.

The TCI6487 features three TMS320C64x+ DSP cores running at 1 GHz. In comparison, its predecessor, the TCI6482, featured a single 1 GHz C64x+ core. TI has also added an antenna interface supporting OBSAI and CPRI protocols.

DSP cores in the TCI6487 communicate with each other and access shared resources by means of a non-blocking switch fabric and a semaphore hardware block. As shown in Figure 1, each C64x+ core features 32 KB of L1 program memory and 32 KB of L1 data memory, and uses a user-selected partition of the 3 MB of L2 SRAM/cache. The DSP cores in the TCI6487 include instruction-set extensions (dubbed "RSA" in Figure 1) to accelerate some CDMA processing tasks. In addition, the chip includes one Viterbi and one turbo decoding coprocessor. It also includes serial RapidIO (SRIO), Gigabit Ethernet, and DDR2 (667 MHz) interfaces.

Figure 1. Block diagram of the TCI6487

According to TI, the software-programmable TCI6487 is binary-compatible with TI's previous C64x+ and C64x-based basestation chips; this will enable migration of legacy software. In addition, an optimized WiMAX software function library and historically strong tools support from TI are likely to make the TI chip attractive to system developers who wish to create their own WiMAX solutions. For further BDTI analysis of the TCI6487 see the full article at Inside DSP.