C6000 vs. PowerPC, part 2: Multiprocessor systems

• VIM Interface – enabled by the C6203's dual external interface, the VIM control/status interface uses the C6203's EMIF, and the C6203's XBUS is used to support the faster BiFIFO interface. Two of the C6203's serial ports are brought up to the VIM connector to provide serial interfaces to I/O modules.

• 16 MByte SDRAM – provides a large, fast memory resource to the processor.

• 1 MByte FLASH – contains processor boot code and provides a non-volatile space for user installed programs.

• Interprocessor Bi-FIFO – a key feature of this design is interprocessor communication provided by Bi-FIFOs between nodes. Any processor can transfer data to its two adjacent nodes through this interface and the C6203's DMA engines allow this to occur with no processing overhead.

• Bus I/O Bi-FIFO – each node has an additional Bi-FIFO connected to a shared global bus. This Bi-FIFO allows data to be shared with any of the board's global resources. Data is transferred to/from this Bi-FIFO by the C6203s DMA engine where it can be later read/written by the global resource, effectively decoupling the node from any global bus traffic.

• PCI Interface – allows the C6203 to access the PCI Bus resources and master the VMEbus through the VME64 interface.

Figure 10

The remaining board architecture is shown in Figure 11. The global resources include a PCI-to-PCI bridge and DMA/memory controller that couples PCI bus 1 to PCI bus 2. Attached to the controller is a flash memory for storing the firmware needed to setup and run the bridge. In addition, is a 32 Mbyte SDRAM used for staging data as it's moved from the node resources in/out to resources on PCI bus 2. On PCI bus 1 is a 100 BaseT Ethernet interface and an RS-232 interface. On PCI bus 2 is a VME 64 interface that provides VME slot-1 controller capability, a PMC module and an optional RACE++ interface.

This block diagram also shows the communication path between processors. Each node's Interprocessor Bi-FIFO connects to it's two adjacent nodes and provides a dedicated path, critical in applications where the data gets pipelined between processors.

(Click to enlarge)
Figure 11