Analysis: Altera jumps to 40 nm with Stratix IV

Altera has unveiled its next-generation high-performance FPGA family, the Stratix IV, and announced that the family will be fabbed in a 40 nm TSMC process. The new Stratix IV chip family will include 12 members: six GX devices, and six E devices. GX chips have from 8-48 high-speed serial transceivers, while the E devices have no transceivers but more memory and more DSP-oriented features. The highest capacity Stratix IV chips will have roughly double the logic capacity of the biggest Stratix III chips—up to 680K logic elements. The new chips will also include up to 22.4 Mbits of internal RAM. Pricing has not yet been announced.

Figure 1. Stratix IV chips. (Data courtesy of Altera)

Stratix IV chips will include hardwired DSP blocks that are somewhat analogous to Xilinx's DSP slices. Each Stratix IV DSP block includes four 18x18-bit multipliers along with other hardware to support multiplication and filtering operations, and runs at up to 600 MHz, according to Altera. The biggest Stratix IV chip will have 340 DSP blocks (1360 18-bit multipliers), compared to 192 DSP blocks on the biggest Stratix III chips.

Unlike Xilinx, Altera doesn't offer an embedded hard processor core like the PowerPC, but it does offer a soft core, Nios II, that can be implemented in the FPGA fabric. Altera will also offer 40 nm "HardCopy" versions of the Stratix IV chips, with initial tapeouts expected in the third quarter of next year.

With its 40 nm, transceiver-equipped Stratix IV, Altera is emphasizing FPGAs' system integration capabilities and scalability, which are key advantages relative to instruction-set processors. As process nodes shrink, FPGA vendors may well get more "bang for the buck" out of each process migration than processor vendors. The challenge for FPGA vendors, of course, is to simplify their application development process as aggressively as they are increasing their chip capacity.

For additional BDTI's analysis on Altera's Stratix IV, see InsideDSP

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