Algorithmic synthesis for video post-processor design

This article describes how ST Microelectronics used Algorithmic Synthesis to design a video post-processor, with the goals of improving project time and design flexibility, without compromising performance and power targets.

Algorithmic Synthesis offers the solution
Engineers can reduce project time and costs significantly if they elevate the design abstraction to an algorithmic level. Algorithmic synthesis (AS) technology allows the creation of complete application engines directly from sequential, untimed C algorithms. This enables the designer to explore multiple algorithms and implementation alternatives with different performance, area and power (PPA) profiles quickly, to find an optimal design and build the hardware automatically.

ST used PICO Express algorithmic synthesis to design a multi standard video post-processor (VPP), an integral part of a multi-standard video CODEC that comprises deblocking and deringing functions. The VPP was selected as a representative example to implement using AS, because it offered the possibility of directly comparing the resulting PPA and time taken with a hand-designed block.

The Critical Role of Application Engines
A typical SoC designed for a consumer device comprises, at the highest level, four different types of IP: complex application engines (e.g. video codecs, wireless modems); Star IP (CPU, DSP); Connectivity and Control IP (USB, DMA); and memory. Typically, the bulk of engineering effort is spent designing and verifying complex application engines, because these are key to defining and differentiating the end product.

Application engines are intricate pieces of IP, usually subdivided into many blocks. Depending on the application, an engine may consist of a control processor and one or more hardware accelerators that help to meet cost and PPA goals. Traditionally, a hardware accelerator is designed block-by-block, either by reusing previously designed blocks, or by designing new RTL blocks manually. The engine is then assembled together, verified, and integrated with the rest of the SoC components.

Application engines created by Algorithmic Synthesis
Algorithmic synthesis creates hardware application engines that "drop" into the rest of the SoC design. Each application engine is derived from a sequential, untimed C algorithm. A designer provides a C description of his algorithm along with a testbench, and defines the design constraints. The PICO system then automatically generates the synthesizable RTL, which is designed to operate at a specific clock frequency and technology target according to the specified constraints.

1. System design flow using algorithmic synthesis that takes untimed C algorithm along with design constraints and delivers RTL, SystemC and testbenches for an optimal implementation in hardware.

As the following test demonstrates, using AS to create the application engine gives the designer unparalleled opportunities for rapid space exploration. AS also automatically creates both a complete RTL verification environment and SystemC transaction level models that can be used for virtual platforms for system validation. In addition, AS produces scripts to drive a variety of tools which ensure a seamless integration into existing RTL-GDSII flows.

ST Project goals
The key goals of this project were to prove that using an AS design methodology can significantly reduce time-to-market and improve responsiveness to change, without sacrificing quality of results (QoR).

PICO Express was chosen for its ability to handle complex designs and deliver good quality results. The VPP was chosen for implementation as a good example of a complex video-processing design supporting multiple video standards, with aggressive performance and area targets.

A design team initially created the VPP by hand. This became the reference design against which the synthesized version would be compared in terms of time (man months) taken to create it and the PPA profile.

VPP features and specification
The filter supports the following video standards for Deblocking and Deringing: H.264, MPEG4, VC1. The VPP also supports upsampling and format conversion.

For this project, the complete VPP was recreated in untimed C. However, the specific PPA to be compared with hand design was the MPEG deblocking filters. From this, it was possible to extract complete VPP PPA and design effort.