USB 2.0 on Blackfin Processors
The competitive nature of the consumer electronics market demands constant innovation, with consumers expecting each new product to be better than the last. One major goal is to create small portable devices that operate for a long time on a set of batteries.
With lower cost ICs and inexpensive development tools, Blackfin processors are helping embedded designers to meet these needs. On the forefront of the effort to provide cost-effective embeddable devices and tools, the ADSP-BF52x processor family is even more powerful than its predecessors, yet it is smaller and consumes less power.
For lower system development costs, the new ADZS-ICE-100B Blackfin emulator, designed with an embedded ADSP-BF527 processor, is an order of magnitude less expensive than previous emulators.
USB 2.0 on Blackfin Processors
Power usage characteristics are important for universal serial bus (USB) devices, and achieving the many benefits of USB requires compliance with published specifications. USB 2.0 allows multiple devices to be connected to a single host with a maximum throughput rate of 480 Mbps.
The low power consumption of the ADSP-BF527 Blackfin processor enables it to offer USB 2.0 capability. Its built in USB physical layer interface (PHY) supports both host and peripheral modes, as well as USB On-The-Go (OTG), which increases product flexibility by allowing a device to swap between host and peripheral, rather than being locked to one type after enumeration.
The USB Implementers Forum (IF) specifies performance criteria and standard tests that a USB-certified device must pass, depending on its intended use. Some of the classifications are low speed (1.5 Mbps), full speed (12 Mbps), and high speed (480 Mbps); and low power (100 mA), high power (500 mA), and self-powered. USB 2.0 compliance also requires adherence to signal quality, timing, and power specifications depending on the device's declared capabilities.
If a device complies with specifications, designers can power their devices directly from the USB port, eliminating external power supplies and their associated extra cost.
To assist embedded developers, a USB certified software stack is included in VisualDSP++ update 8. This software provides a foundation for writing proprietary embedded code for custom designs.
Data exchange and device configurability via PC are the most likely targets, but the software also facilitates interaction with many other consumer electronics devices via USB.
Meeting USB Timing Specifications
USB specifications outline strict timing requirements for device communications. One parameter, SIGATT, specifies that a bus-powered device must signal attachment to the host within 100 ms after the USB voltage (VBUS) reaches 4.1 V. Several key design characteristics help the ADSP-BF527 meet this specification.
The ADSP-BF527 booting process takes a significant portion of the 100 ms allowed by SIGATT. The Blackfin processor starts with preboot code, moving to the desired external boot source based on the state of the boot mode pins.
If the boot mode is set to serial peripheral interface (SPI) flash, the startup time can be limited by the boot SPI clock settings. To alter these settings, one time programmable (OTP) memory can be written to change the system clock (SCLK), core clock (CCLK), and SPI baud rates. Increasing the SPI clock rate at power-up decreases the amount of time it takes to boot the firmware and start USB communications.
Before booting firmware, the ADSP-BF527 requires a reset pulse to allow the internal clocks to stabilize. This reset is triggered by a fixed-duration signal pulse, called the reset asserted pulse width. The reset must conclude before code can be executed, so its duration can contribute significantly to the processor's boot time.
Minimizing the duration of the reset pulse after VBUS is applied to a device enables the processor more time to execute code within the allowed 100 ms. The ADSP-BF527 requires a reset pulse width of 11 clock periods (11 - TCLKIN) after the voltage rails stabilize. This is short enough to ensure that power-up reset does not contribute a significant amount of time to the total embedded system startup.
Clocking a USB 2.0 PHY commonly requires a clock input of 12 MHz or 24 MHz to comply with USB data rates. The ADSP-BF527 interfaces with either a crystal or an oscillator to provide the core clock, but crystals are recommended for low-power designs.
An added benefit of running CCLK at 12/24 MHz is the ability to drive this same frequency out the CLKBUF pin. The CLKBUF output can then be driven back into the USB CLKIN pin of the processor. Implementing this functionality eliminates the need for separate system and USB oscillators, thus reducing the system's component count.