High-def video processing on FPGAs
The demand for higher video resolutions is constantly increasing:
• Video surveillance systems are moving from standard definition (SD) video to high-definition (HD) and incorporating features such as wide- dynamic range (WDR), thus driving the need for higher resolution video processing. This same trend is evident in many industrial imaging systems.
• Broadcast video systems are increasingly moving from 1080p HD resolutions to 2K, 4K and 3D resolutions – to support the next generation cinema and studio requirements.
• Medical imaging systems resolutions are ever increasing – resulting in higher performance signal processing.
Video processing, especially as the world makes a transition to 1080p HD resolution and beyond, is a natural fit for FPGAs. Developing video designs for FPGAs is a time consuming process that can be greatly speeded up by the availability of building block functions, standard video interfaces and reference designs as shown in Figure 3.
The Video Design Framework from Altera includes 18 video functions, a
streaming video interface standard, over half dozen hardware-verified
reference designs, and a range of video development kits.
the Video Design Framework – you can start with existing working
designs, re-use the pre-verified IP for common functions like scaling,
de-interlacing and mixing, add in your custom functions and get the
design done in a fraction of the time it would take to develop a design
Fig. 3: Time-saving design features for video-processing applications
Floating-foint precision: Coming to high-performance DSP
In the domain of high-performance DSP, floating-point signal processing is slowly but surely being looked at as a way to increase the dynamic range. This is happening in systems such as advanced military STAP radar, MIMO equalization for LTE channel cards, and high-performance computing boxes. Research shows the percentage of floating-point signal processing algorithms increasing from 10% of FPGA DSP designs to 20% in 2012.
Floating-point processing generally involves mantissa multiplication, mantissa normalization/de-normalization, and exponent addition. While exponent addition/subtraction is fairly straightforward, mantissa multiplication and normalization requires higher than 24-bit precision multipliers. This can be done by cascading two fixed point DSP blocks or by configuring a single variable precision DSP block in the high-precision mode.
To implement floating point precision, look at the DSP architecture to support floating point mantissa multiplication or mantissa normalization within a single DSP block. Not only will this save resources but will also result in a high performance implementation (i.e. a high fMAX).
FPGA vendors can uniquely take advantage of their architectures and provide a suite of efficient and very high-performance floating point building block IP cores, as shown in Figure 4
Fig. 4: Floating-point building block IP cores
When selecting a FPGA platform for a floating point DSP application, make sure that both the silicon efficiency for floating point operations as well as the availability of building block floating point functions is carefully evaluated. A FPGA DSP architecture optimized for floating point DSP implementation can provide a higher system fMAX and a portfolio of floating point functions can significantly reduce development time.
DSP Solutions provided by FPGA vendors and indeed the solutions required by the markets can and will change over time. Before embarking on a high-performance DSP system design, it would pay (in terms of time-to-market) to evaluate the DSP solutions portfolio offered by the different silicon vendors. Not only would this dramatically improve design/development time, but it also signifies a commitment to the DSP market by the vendor. This is crucial in supporting and updating such high-complexity systems.
About the Author:
Suhel Dhanani is a Senior Manager in the software, embedded and DSP marketing group. Mr. Dhanani is responsible for DSP product marketing. He has over 15 years of industry experience in semiconductors -- with both large companies such as Xilinx and VLSI Technology as well as with Silicon Valley startups including Anadigm and Tabula. Mr. Dhanani has completed a graduate certificate in Management Science from Stanford University and holds M.S.E.E. and M.B.A. degrees from Arizona State University.