Using electronic dispersion compensation to equalize reflections in 8 Gb/s Fibre Channel design

Legacy backplanes generally suffer from distortions due to crosstalk, insertion loss, and multi bit reflections at high-speed data rates. Distortions, in general, are post-cursor in nature but they could be pre-cursor in nature. Pre-cursor distortions can only be equalized by feed forward equalizer (FFE) and can not be equalized by using analog-based equalizer techniques. The post-cursor distortions, because of effects of inter-symbol interference (ISI) and reflections, are corrected with both FFE and DFE.  

Figure 2. The impulse response of the shortest and the longest channels.

As shown in Figure 2 above and Figure 3 below, the multi bit reflections are dominant on the short channels while the insertion loss is dominant on the longest channels of the midplane of interest, respectively. The impulse response of a single bit is shown after the channel in Figure 2 while the insertion loss (SDD21) of the longest and shortest channels are depicted in Figure 3.

Figure 3. The insertion loss (SDD21) for the shortest and longest channels.

Generally, the DFE based receiver might be sufficient to close the link with bit error rate (BER) lower than 1E-15 at legacy FC rates. However, due to reflections and high frequency insertion losses at 8Gbps data rates, the combination of transmit and receiver may not provide enough margin for successful operation. Therefore, an advanced equalizer, such as EDC, is required to null out the reflections and be able to work with attenuated small signals, as shown in Figure 1.

Although the crosstalk due to the midplane and connectors may not be significant, the components on the HBA and switch cards might be a source of crosstalk at high-speed data rates.

Since the footprints of these cards are preset, adding additional components to solve signal integrity challenges must be done with care so that high-speed to high-speed signal coupling is minimized. The power supply noise is another parameter that design engineers need to consider.

It is also important how the high-speed differential signals are routed on both the switch and adapter cards. Because of lack of real estate on the top and bottom of the printed circuit board (PCB), high-speed differential signals must be routed from microstrip to stripline and back to microstrip.

The differential vias used in the transition from microstrip to stripline plays a key role in maintaining constant impedance. In order to keep the impedance constant, ground vias must be used around the differential transition vias to suppress various TE and TM modes.

One of the key techniques in ensuring a constant impedance is to back drill the unused portion of differential vias which eliminates the inherent stub created by that unterminated portion of differential vias between the stripline and far side of the PCB.

While back-drilling is a mature and reliable process, it is also considered to be comparatively expensive and therefore to be avoided if possible. Consequently, the goal is to be cost-conscious although it is critical to mitigate the affects of the stub in the microstrip to stripline transition.