Meeting timing specs on boards with picoseconds of margin

Length-match your traces to within 100 mils. Or is it 10 mils? Or should you go down to 1 mil? Should you include the lengths of the vias? How about the lengths of resistors? Understanding the origin of length-matching requirements, coupled with some rudimentary signal integrity analysis, can help answer these questions.

Determining length requirements requires an understanding of flight time, electrical length vs. physical length, loading and signal quality. Those elements are vital in determining what the length really needs to be, as well as in determining the allowable trade-offs to meet system timing goals.

Length matching

Length-matching requirements exist whenever there is a need for data to arrive at the same time. For a source-synchronous interface like memory, the data must arrive at the receiver at the same time as the clock or strobe, to make sure it is appropriately latched in at the receiver.

For a differential signal, length matching ensures that the two edges of the signal are aligned, and that the signal is truly “differential”—less susceptible to noise and less likely to radiate noise. So, for length-matching a clocking signal to a data signal, the requirement is usually going to be closer to the order of the bit period.

For a 200-MHz clock, the period will be 5 nanoseconds. That yields length-matching requirements on the order of hundreds of picoseconds, which equates to several inches on a printed-circuit board. Differential signals, however, can have edges around 50 ps, so “lining them up” would require skew on the order of 5 ps—around 30 mils on a pc board. That is much less than the skew allowable for maintaining a clock-to-strobe relationship.

Length itself does not determine timing on a pc board. Length has a relationship to delay, but that can vary from layer to layer. So even if the signals travel the exact same length, they may not be lined up with one another in time if they are routed on different layers.

This is most evident when looking at outer layers vs. inner layers. Delay can be calculated using the propagation velocity of the signals, which is a function of the effective dielectric constant of the dielectric material. For FR-4 board material, the dielectric constant is around 4. For air, the dielectric constant is around 1. Since the outer layers are a mixture of both, the effective dielectric constant will be somewhere in between.

The exact numbers can be calculated using a field solver, such as the one contained in HyperLynx.

Figure 1 illustrates the difference in delay between two 1-inch traces. The outer-layer trace has a delay of 148.9 ps; the inner-layer trace has a delay of 168.5 ps. Thus, if there were traces routed on the outer layers that needed to be matched to the inner-layer traces, the outer-layer traces would need to be about 13 percent longer to compensate for the difference in propagation velocity.

Because delay is so dependent on relative dielectric constant, accurate dielectric constant numbers are critical. Getting that information from the board manufacturer is vital to ensuring accurate timing on the board.

Dielectric constant numbers can range from around 3.6 to 4.5 for FR-4 and will vary based on the glass/resin ratio in the dielectric. That means a variance between cores and prepregs, as well as variances among different dielectric thicknesses—a possible discrepancy in delays not only between inner- and outer-layer traces, but also between inner-layer traces on different layers—so it is important to take that into account.

Figure 1. Comparison of inner layer and outer layer trace delays calculated in HyperLynx. Click on image to enlarge.

Figure 2. Calculation of flight time for a 50-ohm trace, with waveform from a 21-ohm trace shown for comparison. Click on image to enlarge.