Meeting timing specs on boards with picoseconds of margin

Impedance is also important in determining system timing. Too often, impedance is overlooked in timing calculations, which can lead to large errors in the design.

Impedance is important in that it shapes the received waveform. The shape of received waveforms, in turn, determines when the waveform crosses logic thresholds. Therefore, impedance is just as crucial as delay in determining system timing.

In fact, both delay and impedance are included in a metric called flight time, which is basically a measurement of the time between when a signal is launched and when it is received.

The receiver waveform is compared against a test load waveform, which is designed to mimic the driver waveform and tie in the on-chip timing.

Figure 2 shows an example of flight time. In this simple schematic, a driver is connected to a receiver by a 10-inch trace. Notice that the delay of the trace is 1.685 ns (shown underneath the transmission line symbol) but the calculated flight time is between 1.531 ns and 1.683 ns (lower left). This is because the flight time calculation includes the time it takes to hit both logic low- and logic high-voltage thresholds, as well as accounting for the effects of impedance.

To illustrate the effect of impedance further, the trace was widened to 30 mils. That decreased its delay by 10 ps but also reduced its impedance, to around 21 ohms. Because the impedance changed, the received waveform crossed the high logic threshold 40 ps before the original waveform, which had the 50-ohm line. (This is shown by the cursors in Figure 2.) Thus, the impedance had a clear effect on the flight time.

The effect of impedance is also evident when including the timing effects of vias. As shown in Figure 1, outer- and inner-layer traces can have very different delays. But when routing to those different layers, the designer will also need to use vias, which have their own delay properties beyond just their simple length.

Designers often include via length in their length-matching analysis to be “extra precise.” But what should really be included is the delay through the via, as well as the effect of its impedance on the received waveform.

Figure 3 shows simulations of two via models. Via V1 goes all the way through the board, a distance of 80 mils. Via V2 goes from the top to the InnerSignal1 layer, a distance of 11 mils. Via V1 adds about 28 ps to the flight time of the signal passing through it, whereas V2 adds about 7 ps, for a difference of 21 ps.

Compare those numbers with the delay through 80 mils of trace, which would be about 13 ps, or even 11 mils of trace, which would be about 1.8 ps, and it becomes clear that the time added by the vias is much different and will vary from via to via. Signals do not propagate through vias the same way they do along traces.

Via impedance also typically differs from that of traces. Even though one via may be much shorter than another, it may still impose additional flight time variance because of its stub, which will act like an impedance discontinuity and degrade the edge of the signal passing through the via.

Figure 3. Effect of different vias on signal flight time. Click on image to enlarge.

Figure 4. Timing variance caused by different resistor values. Click on image to enlarge.