Gigabit serial links: Gateways to multicore scalability

As multicore processors benefit increasing numbers of high-performance, data-intensive applications, such as wireless basestations and high-performance compute platforms, system scalability can only be achieved through high-capacity embedded interconnect. Gigabit serial links help enable system scalability by reducing system cost, area footprint and pin count while delivering greater parallelism, performance and capacity.

Gigabit serial links define the physical layer of the high-speed communication link. The serializer/deserializer (serdes) at the heart of the gigabit serial link transforms the parallel data inside the device into serial data streams for communication to the external world. Compared with parallel interfaces, serdes-enabled serial links shrink the device area and package size while reducing cost and power consumption, enabling higher system performance.

Figure 1 offers a high-level overview of serdes operation. In the transmit direction, the byte serializer converts parallel bits into serial bytes, then encodes them before sending them out to the serial links. 

The most common encoding scheme is 8b/10b, which maps 8-bit data bytes to 10-bit code by adding clock and framing control information so the receiver can recover that information and align it with the transmit data.

In some cases—such as for 10-, 40 and 100-Gbit/second Ethernet—64b/66b encoding is used to enable increased data payload throughput.

In the receive direction, the serial input is first decoded by an 8b/10b or 64b/66b decoder. It then is fed into a clock and data recovery (CDR) block to synchronize with the transmit clock and framing before being sent to the deserializer for conversion to parallel data for internal processing.

Figure 1. The serializer/deserializer is the foundation of gigabit serial links. Click on image to enlarge.

Many communications protocols can be built on top of the serdes function for various data-intensive applications. Figure 2 shows a typical system-on-chip integrating the CPU and digital signal processor, as well as hardware accelerators for application processing. Gigabit interconnects that can be built on top of the serdes function include Gigabit Ethernet, Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI), JESD204B, Serial RapidIO and PCI Express (PCIe).

Figure 2. Communications protocols can be built on top of the serdes function in data-intensive applications. Click on image to enlarge.

These interconnects greatly enrich SoCs for today’s high-performance computation needs.