Energy harvesting: A battle against power losses

Pre-charge:
During the pre-charge phase, the cumulative resistance between C_BAT and C_MEMS, that is, the parasitic ESRs and CMOS channel resistances in the current-flowing path, induce a power loss term that is dependent on how often the current is switched through,

(3)

where P_Condis averaged over time, I_L,RMS is the root-mean square (RMS) value of the inductor current, R a resistance in the current-flowing path, _Cond the total conduction time, and fVib the vibration frequency. Current IL,RMS always flows through R_{ESR_L}, two MOS switches, and one of two other ESRs, and assuming all switch-on resistances (including the parallel combination of MP₄ -MN₄) equal and R_{ESR_BAT} and R<> are about the same, the total conduction losses are

(4)

where N is the number of inductor storage-delivery cycles within the pre-charge phase, R_ESR,BC the ESR of the battery and C_MEMS, and _L the storage and delivery time within one cycle.

Overlapping the conduction bands of any two interconnecting but oppositely phased switches from supply to ground consumes considerable short-circuit power and a dead time must therefore be inserted in the driving signals. Devices MP₁ and MN₂ and MN₃ and MP₄-MN₄ are two such sets of devices. When MP₁ and MN₃ turn off, to be specific, current must first flow through MN₁'s body diode, R_{ESR_L}, MP₄'s body diode, and R_{ESR_MEMS} for dead time _Dead before MN₁ and MN₄-MP₄ are allowed to conduct, incurring additional conduction power losses,

(5)

where dead time current I_L,Max is the peak inductor current (assumed constant during _Dead) and V_Diode the voltage drop across each body diode.

As each switch turns ON or OFF, the parasitic gate and drain capacitors of the MOS devices must charge and discharge, both events of which require switching power. The average gate-power lost per switching event (turn-ON or -OFF), for instance, for a parasitic gate capacitor (C_g,Par) is

(6)

where V_Drive is the peak voltage change across the capacitor (normally V_Bat) [3]. This power is consumed by the stage that drives C_g,Par, not the transistor itself. Similarly, as each switching event takes place, parasitic capacitors present at the drain (C_d,Par) must also charge and discharge. In this latter case, however, the switching transistor dissipates the switching power, as it concurrently conducts drain current with a high drain-source voltage. The resulting average I-V overlap (or drain-charge) power loss per switching event is

(7)

where V_Peak is the drain-source voltage of the switch before turning ON (equal to V_Bat in the case of MP₁ and MN₂). The drain-source voltages of MN₃, MN₄, and MP₄ are close to zero (within a diode voltage) before they are turned ON because their respective body diodes discharge their drain-source capacitors during dead time. These latter transistors consequently operate in zero-voltage switching (ZVS) conditions, which incur considerably lower switching losses [4]. In the end, small geometry devices (low C_g,Par and C_d,Par values) are preferred for lower switching power losses, but only when the gate-drive and drain-charge losses in (6) and (7) overwhelm the gate-drive dependent switch-on resistance conduction losses in (4), all of which is ultimately a strong function of the battery voltage (peak voltage transitions).