Power losses generally come in the form of conduction and switching losses. Parasitic diodes, resistive CMOS switches, and ESRs, for instance, incur I2
R and IV conduction losses. Parasitic capacitors present at the gates and drains of CMOS transistors, on the other hand, require power to charge and discharge, and this is how switching power losses result. Overlaps in the conduction bands of interconnected but oppositely phased switches from supply to ground also introduce additional short-circuit I2
R conduction losses, but these are reduced by introducing dead bands. For the purposes of the foregoing discussion, power losses will be analyzed in each of the three phases of the circuit: pre-charge, harvesting, and recovery phases.
During the pre-charge phase, the cumulative resistance between CBAT and CMEMS, that is, the parasitic ESRs and CMOS channel resistances in the current-flowing path, induce a power loss term that is dependent on how often the current is switched through,
where PCondis averaged over time, IL,RMS is the root-mean square (RMS) value of the inductor current, R a resistance in the current-flowing path, Cond the total conduction time, and fVib the vibration frequency. Current IL,RMS always flows through RESR_L, two MOS switches, and one of two other ESRs, and assuming all switch-on resistances (including the parallel combination of MP4 -MN4) equal and RESR_BAT and R<> are about the same, the total conduction losses are
where N is the number of inductor storage-delivery cycles within the pre-charge phase, RESR,BC the ESR of the battery and CMEMS, and L the storage and delivery time within one cycle.
Overlapping the conduction bands of any two interconnecting but oppositely phased switches from supply to ground consumes considerable short-circuit power and a dead time must therefore be inserted in the driving signals. Devices MP1 and MN2 and MN3 and MP4-MN4 are two such sets of devices. When MP1 and MN3 turn off, to be specific, current must first flow through MN1's body diode, RESR_L, MP4's body diode, and RESR_MEMS for dead time Dead before MN1 and MN4-MP4 are allowed to conduct, incurring additional conduction power losses,
where dead time current IL,Max is the peak inductor current (assumed constant during Dead) and VDiode the voltage drop across each body diode.
As each switch turns ON or OFF, the parasitic gate and drain capacitors of the MOS devices must charge and discharge, both events of which require switching power. The average gate-power lost per switching event (turn-ON or -OFF), for instance, for a parasitic gate capacitor (Cg,Par) is
where VDrive is the peak voltage change across the capacitor (normally VBat) . This power is consumed by the stage that drives Cg,Par, not the transistor itself. Similarly, as each switching event takes place, parasitic capacitors present at the drain (Cd,Par) must also charge and discharge. In this latter case, however, the switching transistor dissipates the switching power, as it concurrently conducts drain current with a high drain-source voltage. The resulting average I-V overlap (or drain-charge) power loss per switching event is
where VPeak is the drain-source voltage of the switch before turning ON (equal to VBat in the case of MP1 and MN2). The drain-source voltages of MN3, MN4, and MP4 are close to zero (within a diode voltage) before they are turned ON because their respective body diodes discharge their drain-source capacitors during dead time. These latter transistors consequently operate in zero-voltage switching (ZVS) conditions, which incur considerably lower switching losses . In the end, small geometry devices (low Cg,Par and Cd,Par values) are preferred for lower switching power losses, but only when the gate-drive and drain-charge losses in (6) and (7) overwhelm the gate-drive dependent switch-on resistance conduction losses in (4), all of which is ultimately a strong function of the battery voltage (peak voltage transitions).