High-Voltage CMOS process features galvanic isolation for smart-energy designs

By Markus Wuchse, Marketing Manager; Helmut Hofstaetter, Foundry Engineer; Hubert Enichlmair, Process Development & Implementation Engineer

Numerous applications such as sensor interfaces, actuators, power management ICs (integrated circuits) or display drivers must be able to switch voltages beyond 5 volts. For those applications, a new high-voltage CMOS process,  austriamicrosystems’ H35, allows designers to integrate transistors in several voltage domains -- ranging from 3.3 V up to 50 V and even up to 120 V -- on a single piece of silicon. Only two additional mask levels to its standard 0.35 µm CMOS process are required and results in a process that allows designers to achieve size-optimized architectures combined with the lowest device complexity.

However, there are an increasing number of complex analog/mixed-signal applications that cannot be integrated into a monolithic system, at least not yet. For example, in the case of switching-mode-power-supplies (SMPS) and motor drivers, two individual ICs must be functionally synchronized, even though they are operated at significantly different voltage levels (e.g. at 0 V and 200 V). See figure 1. Therefore, dedicated communication channels have to be established between these two circuit domains in order to achieve synchronized performance. On the one hand, these communication channels have to sustain the maximum voltage difference between the domains, while on the other hand they also have to ensure sufficiently high data rates for the exchange of the required information.

At present, isolated communication is typically achieved by using an optocoupler or a transformer placed on the PCB between the two voltage domains. See figure 1. Both types of components are known for their high electrical strength and reliability. However, the downside is that both optocouplers and transformers take up additional space on the systems’ board and certainly need notable power for their operation. Plus they add cost and complexity to the system BOM.

Figure 1. Motor controller with high-side and low-side driver operating at two different voltage domains sharing information by means of a discrete isolating component.

In order to shift the isolation from board to device level, some products currently utilize additional post processing steps. That is, thick polymeric redistribution layers are added on top of the IC, because standard inter-metal dioxide layers in conventional CMOS processes cannot provide the electrical strength required. So, depending on the targeted isolation levels, these redistribution layers have thicknesses of 10 µm and more. The newly developed galvanic isolation process from austriamicrosystems goes one step further. It allows designers to skip additional isolating components on the PCB as well as costly post processing steps and to directly integrate the fully isolated communicating circuits into one single package (i.e. dual-die solution).

With this approach, a motor controller (ref. to figure 1) may be realized by a single component comprising two individual die (i.e. the high-side and the low-side driver) within one package. See figure 2. Even though the two die are operated at voltage levels differing by 200 V or more, they still can share information by means of capacitive or inductive coupling. The required electrical isolation is immediately given, when at least one of both ICs comprises austriamicrosystems’ special inter-metal dioxide (IMD).

Figure 2. Dual-die solution for galvanic isolation between IC1 and IC2 using a special IMD for isolation between separate metal layers. Data can be transferred from transmitter to receiver coils.

This special IMD is austriamicrosystems’ latest extension of its specialty High-Voltage CMOS technology portfolio. Without changing the standard bill of materials, but instead utilizing a low stress oxide, austriamicrosystems now has the capability to increase the IMD thickness for increased electrical strength between separate metal layers. As an example, with its H35B4V1 process extension the IMD thickness has been increased by a factor of approximately 1.8 compared to its standard H35-IMD process, which provides galvanic isolation levels exceeding several 100 Vrms. Conservative evaluations based on first engineering runs of the new process revealed electrical strengths of 460 Vrms minimum between metal1 and metal4 lines respectively, and 610 Vrms between substrate and metal4.

Based on a series of accelerated-stress TDDB testing (i.e. time-dependent dielectric breakdown testing), the lifetime for these ratings can be predicted to be a minimum 10 years at 150°C. According to the conservative lifetime model, the time to failure (TF) relates to the electric field at a certain temperature as the following equation shows:
log(TF) ~ γ * E, where γ is the voltage acceleration factor and E is the electric field in the oxide. The TF- values are determined according to the Weibull statistic (10 ppm) for a series of electrical stress fields at the maximum operating temperature. The lifetime can be extrapolated for lower electrical fields, which correspond to the operating voltage. For voltage peaks (i.e. 100 seconds at 150°C), the preliminary ratings read 3.4 kVrms and 4.3 kV between M1 and M4 respectively, and between substrate and M4

These ratings refer to so-called single-isolated systems -- see figure 2. In these cases only one IC within the dual-die solution uses the special IMD. That is, the high-side driver (i.e. IC1) may be simply based on austriamicrosystems’ high-voltage CMOS processes, while the low-side driver’s architecture (i.e. IC2) needs to use a signal transmitter coil at metal4, which is electrically isolated from the receiver coil at metal1.

When higher voltage ratings are required, a designer may consider either the implementation of higher IMD thicknesses or simply design-in double-isolated systems. In the latter case -- for example the high-side and the low-side motor driver -- both ICs need to use inductively or capacitively coupled communication paths. Figure 3 illustrates the physical separation from each other by austriamicrosystems’ IMD-layer. This approach will immediately lead to a system featuring electrical strengths twice as high as single-isolated systems. As an example, when both ICs feature isolated capacitor planes on metal1 with respect to metal4, the overall voltage rating will exceed 900 Vrms (for 10 years at 150°C), as the electrical strength is doubled

Figure 3. Example of doubling the electrical strength of the dual-die solution by means of a series connection of two capacitors.

There are many sustainability initiatives being developed around the globe these days. While governments and corporations are trying to reduce their CO2 footprint by consuming less energy, they are concurrently striving for alternative, green energy sources such as solar power. ICs based on austriamicrosystems’ H35B4V1 will be perfectly suited to operate solar panels in a highly efficient way. The process allows the design of smart power management ICs that monitor solar panels operating at voltage levels up to 50 V. On the other hand, it provides the possibility to integrate a direct feedback loop from the power grid to the controller unit, as it is able to isolate grid voltages up to several hundred volts. See the simplified diagram in figure 4.

Figure 4. Solar inverter using a micro inverter for DC/AC-power conversion. In this example, the feedback loop has the galvanic isolation fully integrated within the analog V/I-sensing unit.

This new semiconductor process offers a compelling alternative to traditional techniques of achieving galvanic isolation. Designers can reduce cost, complexity and size in many applications. In addition, the simpler system complexity is inherently more reliable and should be considered for smart-energy designs in industrial, automotive and medical applications.