XILINX SPARTAN TECHNOLOGY
To meet the demands of industrial product design, companies like Princeton Power Systems leverage flexible development vehicles such as Xilinx’s Targeted Design Platforms (TDPs), with their rich ecosystem of design services support. In this case, however, the engineering team faced an initial challenge of determining how to expand the inputs and outputs of the DRI system’s digital signal processor, and how to implement control and communication interfaces that functioned in parallel. PDS Consulting offers design services in programmable digital systems for a variety of markets including aerospace and defense, broadcast, industrial, scientific and medical. The firm supported work on the project as a member of Xilinx’s Alliance Program.
The PDS Consulting team provided on-site, hands-on system debug and PCB bring-up, as well as off-site RTL and IP design services. We also advised Princeton Power Systems developers on how to implement the system control interface for their green power control algorithm. In the end, engineers chose a Xilinx Spartan XC3SD3400A FPGA married to a DSP as a prime system control component (Figure 3
Figure 3 – Engineers chose a Spartan-3A FPGA, with its extensive SelectIO capabilities, as the main system peripheral.
The Spartan-3A FPGA, with its SelectIO capabilities, offered flexibility in implementation, particularly for trigger signals and ADC input channels. Xilinx’s Spartan-3A family is a superior alternative to mask-programmed ASICs because these FPGAs permit design upgrades in the field and avoid the high initial cost, lengthy development cycles and inherent inflexibility of conventional ASICs. The integrated technology afforded by the Spartan-3A made the implementation of Princeton Power Systems’ patented control algorithm for green power conversion a possibility.
It took more than 300 I/Os to implement the DRI system interface, which enabled access to 8 Mbytes of flash, a 256-Mbit SDRAM and USB/RS-232 at >900 kbits/second. In addition, the team also utilized the generous amount of fast, distributed 32-bit dual-port RAM inherent to the Spartan architecture. The configurable logic block (CLB) lookup tables used as dual-port RAMs enabled the efficient local storage of new energy waveform samples that the ADCs supplied, while the DSP read the previous samples and a PicoBlaze embedded processor analyzed new values from the second port concurrently.