Sepic converter with Rwire compensation
Voltage drops in wiring and cables can cause load regulation errors. These errors can be corrected by adding remote sensing wires, but adding wires is not an option in some applications. As an alternative, the LT3796 can adjust for wiring drops, regardless of load current, provided that the parasitic wiring or cable impedance is known.
shows a 12V SEPIC converter that uses the RWIRE
compensation feature. RSNS1 is selected to have 1A load current limit controlled by the ISP, ISN pins. The resistor network R1–R5, along with the LT3796’s integrated current sense amplifier (CSAMP in Figure 7
), adjusts the OUT node voltage (VOUT
) to account for voltage drops with respect to the load current. This ensures that VLOAD
remains constant at 12V throughout the load range.
Figure 6: This SEPIC converter compensates for voltage drops in the wire between the controller and the load (RWIRE)
Click on image to enlarge
shows how the LT3796’s internal CSAMP circuit plays into the operation. The LT3796’s voltage loop regulates the FB1 pin at 1.25V so that I3
stays fixed at 100µA for R5 = 12.4k. In Figure 7
changes with current I2
= 1.25V + I2
• R4. If the change of I2
• R4 can offset the change of ILOAD
• (RSNS1 + RWIRE
), then VLOAD
will stay constant.
Figure 7: RWIRE voltage drops are compensated for via the LT3796’s CSAMP circuit
Referring to Figure 7
, the divider R1/R3 from VOUT
sets the voltage regulated at CSP by the current I1
flowing in R2. I1 is conveyed to the FB1 node where it sums with I2
As the output current increases, I1
decreases due to the increasing voltage drop across RSNS; its decrease must be compensated by a matching increase in the current I2
to maintain the constant 100µA into FB2. This increase in I2
with output current is what gives VOUT the positive load regulation characteristic. The positive load regulation is just what is needed to compensate for the cable drop.
The measured VLOAD
with respect to ILOAD
are shown in Figure 8.
is independent of ILOAD
is less than the 1A current limit. When ILOAD
approaches 1A, the current loop at ISP and ISN pins begins to interfere with the voltage loop and drags the output voltage down correspondingly. The load transient response is shown in Figure 9
Figure 8: Measured VLOAD and VOUT with respect to ILOAD drops are compensated for via the LT3796’s CSAMP circuit
Figure 9: Load step response of the circuit in Figure 6