Editor's Note: This paper was selected as a 2012 DesignCon Paper Award Winner in the High-Speed Design category. For more papers, technical discussion, and exhibits about high-speed design, visit DesignCon 2013.
Complex digital systems such as high performance computers (HPCs) make extensive use of high-speed electrical interconnects, in routing signals among processing elements, or between processing elements and memory. Despite increases in serializer/deserializer (SerDes) and memory interface speeds, there is demand for higher bandwidth busses in constrained physical spaces which still mitigate simultaneous switching noise (SSN). The concept of zero sum signaling utilizes coding across a data bus to allow the use of single-ended buffers while still mitigating SSN, thereby reducing the number of physical channels (e.g. circuit board traces) by nearly a factor of two when compared with traditional differential signaling. Through simulation and analysis of practical (non-ideal) data bus and power delivery network architectures, we demonstrate the feasibility of zero sum signaling and compare performance with that of traditional (single-ended and differential) methods.
Many digital systems such as High Performance Computers (HPCs) make extensive use of both differential and single-ended channels and busses. For example, high-speed differential serial channels are often used for processor-processor communications, while dense single-ended busses are typically used for processor-memory interfaces. Differential signaling has many advantages (e.g. common-mode noise rejection, reduced simultaneous switching noise (SSN), etc.), but uses twice the number of interconnect traces as single-ended signaling. We propose that an intermediate solution might be optimum. Consider a set of buffers driving 2N interconnect traces, where at any given time, N of these traces are in a logic high state (sourcing current), and the other N of these traces are in a logic low state (sinking current), but without the restriction that a differential system would have (i.e., that the high and low state pairs must be adjacent).
We call this “zero sum signaling” as it preserves one of the most important features of a differential buffer system – the constant supply current sourcing independent of the output states. This constant current feature translates into greatly reduced switching current transients interacting with system inductance, and hence lower power supply voltage transients and associated data corruption. Using single-ended traces and a suitable coding scheme to create a balanced (or even nearly-balanced) number of logic high and low states across the bus at any point in time, it is possible to transmit more data down the 2N traces than would be possible with a differential signaling protocol, approaching the single-ended limit as the bus size (N) grows.
We begin this paper with a brief theoretical discussion of the zero sum signaling method. We then detail the coding methodology and generate sets of balanced and nearly balanced code words. Next, using time-domain simulations, we evaluate the feasibility of zero sum signaling as applied in a notional, HPC environment including realistic active and passive elements.
Within the simulation section, we explore a number of variations to the operating conditions and observe the impact to the high-speed link performance. Performance is evaluated using nominal and more stressful bit pattern stimulus conditions across a parallel bus while monitoring metrics such as vertical eye opening at the end of the links. The paper is completed with conclusive remarks and suggestions for additional effort.
Zero Sum Signaling Basic Principles of Operation
Three different parallel bus data transmission methods are considered throughout this paper; single-ended (SE), differential (DIFF) and zero sum (ZS). Given a fixed number of printed wiring board (PWB) traces, the number of data bits that can be transmitted using the three signaling schemes is explored in Table 1 below. Note that the formula shown in the table for the number of zero sum bits comes from counting the number of codes available with 2N total bits in which N bits are ones and N bits are zeroes. As N grows, the number of zero sum data bits approaches the single-ended data bit limit.
Table 1: Comparison of Single-ended, Differential, and (optimal) Zero Sum Signaling Schemes.
Obviously, for binary transmission, the non-integer ZS data bits in Table 1 are non-physical. Alternatively, we can effectively invert these formulae to compute the number of traces that would be required to carry a fixed number of bits using these signaling schemes. The results of these formulae are showing in Table 2 below. For the zero sum case, we restrict ourselves to an even number of traces (as otherwise an equal number of ones and zeros is not possible), computing the smallest even integer number of traces which can support the given number of data bits.
Table 2: Traces Required for Various Signaling Schemes In Order to Support a Fixed Number of Data Bits.
A block diagram comparing notional single-ended, differential, and zero sum links for a 32 bit data bus is shown in Figure 1.
Figure 1: Comparison of Traditional Signaling Schemes (Single-ended and Differential) and Zero Sum Signaling. (23489v3)