A zero sum signaling method for high speed, dense parallel bus communications

Note that this concept can be extended to incorporate “nearly zero sum” encoding schemes. In this case, the number of zeroes and ones is not restricted to be equal, but may differ by some finite “disparity”, d (e.g. d=±2, ±4, etc.). This situation would result in finite current switching and hence increased SSN, but with the benefit of an expanded set of code words, and hence more theoretically available bits for a given number of wires. Even though we are expanding the notion of zero sum signaling to encompass nearly zero sum codes, we will continue hereafter to use the term “zero sum signaling” to refer to the general concept in both cases, using the term “disparity” to reflect the allowed difference between the number of zeroes and ones across the zero sum bus at any given instant in time.

The formula in Table 1 for computation of the number of (encoded) bits which can be carried across a given number of traces can be extended to accommodate finite disparity as follows. The number of code words available across 2N bits which have exactly N-k ones and N+k zeroes (i.e. the code words with a disparity equal to 2k) can be computed as follows:

Equation 1

The same formula applies to the number of code words with N+k ones and N-k zeroes. One computes the number of effective bits available through the use of all code words by adding up the total number of code words with disparity, d, less than or equal to a given value and taking the log base two of this number. For example,

Equation 2

In Table 3 below, we apply these formulae to compute the number of data bits which can be supported across a range of assumed physical interconnect traces using zero sum signaling with a range of allowable disparities (abbreviated as “ZS ±d”). Note that in parenthesis, we represent the integer part of this computed number, as generally one is only interested in using a bus to transmit an integer number of bits per word. For comparison, the number of single-ended (SE) and differential (DIFF) data bits are shown as well.

Table 3: Data Bits Supported for Various Signaling Schemes Across a Fixed Number of Traces.

Again, we can invert these formulae to compute the number of traces that would be required to carry a fixed number of bits using any of these signaling schemes. The results of these formulae are showing in Table 4 below. As before, we compute the smallest even integer number of traces which can support at least the given number of data bits. Note that allowing finite disparity does open up the code space such that additional bits can be carried, but that the restriction to even integer numbers of traces is such that the incremental code space allowed by ZS±4 does not allow a reduction in trace count relative to ZS±2 (at least for the cases considered in the table).

Table 4: Traces Required for Various Signaling Schemes (Including Zero Sum with Finite Disparity) In Order to Support a Fixed Number of Data Bits.

Before proceeding with the simulations, it was necessary to investigate the methods of generation of zero sum coded data, as will be described in the next section. The following sections will then describe the simulation details and conclusions.

Zero Sum Coding
In order to implement the zero sum signaling concept, either in simulation or hardware, it is necessary to encode and decode arbitrary data words to and from a set of balanced code words, where the code words contain an equal number of zero and one bits. Substantial research has been done on balanced encoding and decoding [1], [2], [3], [4], [5] with a variety of applications, including data transmission and storage. Balanced coding for data transmission generally supports the goals of transition density and DC-free characteristics that are desirable for both electrical and optical links. Some coding techniques also address data integrity and error detection and correction.

Popular transmission encoding techniques such as 8b10b address the needs of a stream of bits transmitted over a single serial channel. The 8b10b code is not perfectly balanced, but ensures that the disparity in a stream of 20 bits is no more than 2, and that there are no more than five ones or zeroes in a row. Zero sum encoding, on the other hand, must address a parallel data “word,” ensuring that there are an equal number of zero and one bits simultaneously transmitted over a data bus. Therefore, alternative encoding/decoding schemes and alternative hardware implementations are needed for zero sum encoding.

For the purposes of this paper, the main requirement was that a method of providing coded data for simulations could be developed. This task is relatively straightforward, as there were no particular limitations on the computing resources that could be employed for this purpose. Support of coding for simulation purposes is discussed in the next section. Of course, practical implementation of zero sum signaling would require an efficient hardware implementation of an efficient coding scheme. This is a much more difficult problem to solve, and was beyond the scope of the work performed for this paper.