Traditionally, a processor supporting different computing cores in symmetric/asymmetric architectures typically boots from a specific core generally designated as either master or core 0. In this era of economic slowdown, semiconductor companies have been innovating different approaches to be more cost effective and improve their gross margins.
SoC solutions are designed to meet the requirements of multiple domains. Allowing asymmetric booting enables the companies to expand the targeted range of the SoC to various markets using the same lithographic masks. For example, if an SoC has an AP (Application Processor) and an RTC (Real Time Controller) core, then allowing SoC to boot from either AP or RTC enables the same SoC to be used both in high performance applications using AP boot and mission-critical low latency, time critical application using RTC boot.
The desire for building a connected world has created unique system architecture designs. These designs range from unicore systems to multi-core architectures using homogeneous or heterogeneous computing architecture. Complex applications designed today require support for specific hardware accelerators performing a dedicated function in the system. These are implemented in the form of ASICs, FPGAs, GPUs, and the like. These different functional units mostly follow different ISAs (Instruction Set Architectures).
What are asymmetric cores?
Asymmetric cores refer to a system with two or more processing elements or units having different ISAs. These cores provide specific functionality to the overall system such as improvement in the processing power or improvement in the reaction time of the system.
Figure 1. An asymmetric multicore SoC boosts system performance but can present challenges in creating a suitable boot architecture.
Consequently, system software design with asymmetric cores becomes a challenge. The problem is further complicated when the SoC supports booting from multiple cores.
Design criterion for boot architecture
Various challenges are encountered when defining the boot architecture in such systems. Not every problem has a generic solution, and sometimes a solution also requires support from hardware. The next sections describe are few design challenges encountered in defining a suitable boot architecture:
- ISA compatibility
- Power-on reset vector location