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agk

12/18/2011 1:27 AM EST

All the life for the EE's this has been a challenging task.We live with it. ...

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상호

12/15/2011 3:43 AM EST

nice article

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Jitter and timing analysis in the presence of crosstalk

Chris Loberg

12/14/2011 6:42 AM EST

Serial data standards continue to proliferate, providing dramatic improvements in PC and Server system performance. Testing these higher speed standards for evidence of jitter is critical for long-term stability and to achieving the objective of a good Bit Error Ratio (BER) in the design.  Effective analysis begins with selecting the right instruments and have a good understanding of instrument noise, rise time and factors such 3rd, 4th, 5th harmonic performance.

But it’s more than just taking the measurement -- the proper instruments need to be paired with the proper analysis tools.  And other factors such as jitter separation, and de-embedding/embedding are also important considerations when testing serial data rates beyond 8 Gb/sec.  For this article, we will focus on a new approach to jitter separation in the presence of crosstalk, a growing problem as the number of lanes increases to boost computing system throughput.

All electrical systems that use voltage transitions to represent timing information have timing jitter. Historically, electrical systems have lessened the ill effects of timing jitter (or, simply jitter) by employing relatively low signaling rates. As data climb above 8 Gb/sec., jitter has become a significant percentage of the signaling interval, and understanding the types and sources of jitter is vital to successfully deploying high-speed serial technologies.

At its simplest, jitter is a deviation of an edge from where it should be as shown in figure 1.  As the ITU defines it, jitter is “short-term variations of the significant instants of a digital signal from their ideal positions in time.”

Click on image to enlarge.
Fig 1: Jitter is the deviation of an edge from where it should be.


There are several ways in which jitter can be measured on a single waveform including period jitter, cycle-cycle jitter, and time interval error (TIE), and the design will often dictate which measurement is appropriate.

In the case of a stand-alone oscillator, the signal is a clock and it can be hopping or swept. Here period jitter is an appropriate measurement. In the case of a transmitter for a serial data stream, the signal is a data stream and ISI (inter-symbol interference) is a key problem.  Here TIE jitter is the appropriate measurement.

The engineer on the prowl for jitter issues has a number of instruments available, each with unique strengths and weaknesses:
  • A real-time digital storage oscilloscope (DSO) recovers the whole waveform and can measure anything and can be used for TIE, cycle-to-cycle and period jitter measurements. It has limitations, however, around frequency (or bit rate) and resolution of spectra, minute jitter and multi-level modulation.
  • A BER Tester (BERT) is well suited for TIE jitter, particularly TJ or total jitter, a form of TIE. The advantage of the BERT is that is counts every bit, but the tests can be time consuming to perform.
  • A real-time spectrum analyzer (RTSA) can be used for cycle-to-cycle and period measurements with complex modulations for mobile devices, looking at clocks, PLLs and understanding their dynamic performance.  Limitations include span (sub-100 MHz) and bandwidth signals with large modulation spectrum
  • Equivalent-time sampling oscilloscopes offer the best bandwidth and can be used for all jitter measurements for serial data.  Currently, these are the only instruments with noise analysis and a BER eye. Limitations include no real-time capture and can only be used for repetitive patterns and some jitter spectra are aliased.
One question that often comes up is why worry about jitter if ultimately we’re only concerned about the BER.  The reason is that too much closes the eye (in width) which leads to errors. Jitter and noise analysis are simply tools that let you quickly predict and analyze problems in the BER. Ultimately, it is all about the errors, but eliminating those errors in a design requires insight into the cause or causes of excessive jitter.

The place to start is to gain an understanding of how the system performs from an overall BER perspective. The oscilloscope accomplishes this using eye diagrams and statistical analysis to create a bathtub plot, so named because of the shape of the resulting chart as the limits change. With the BERT instrument the result is a jitter peak graph resulting from an exact count of every bit.  As shown in figure 2, the jitter peak from the BERT on the left and the oscilloscope jitter bathtub plot are nearly an exact equivalent.
 

Click on image to enlarge.

Fig 2: Equivalent view of BER performance between BERT jitter peak on the left and oscilloscope jitter bathtub on the right.

Given the close alignment in results, the oscilloscope is a very useful complement to the BERT, since the measurement of TJ to the BER=10-12 can take hours using a BERT and the result doesn’t reveal what kinds of problems are causing the jitter.  The oscilloscope can measure a small amount of data in smart way and then can break the jitter into jitter components typically following the accepted jitter model shown in figure 3.

By making assumptions, the oscilloscope can make TJ@BER calculations that mirror the results obtained using the BERT in a fraction of the time – that is, if all the assumptions are true.  All models of complex systems make assumptions and simplifications, so the fit between the model and the true system behavior will never be exact. As discussed in the remainder of this article, a particularly daunting problem to date has been crosstalk.
 

Click on image to enlarge.
Fig 3: The industry’s jitter model 2001-2010.




EREBUS

12/14/2011 5:25 PM EST

Good overview of high speed cross talk issues.
Thanks

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상호

12/15/2011 3:43 AM EST

nice article

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agk

12/18/2011 1:27 AM EST

All the life for the EE's this has been a challenging task.We live with it. Every time a new advancemnt is taking place in the component level to reduce noise and jitter. Ideally speaking suppose the clock generator and the digital logic circuits are let us say ideal has zero raise,fall and delay time, then, only the noise and disturbance added by the tranmisson media to be accounted. But the possibility of making such a situation is remote. Till then we need to depend upon all the error correcting techniques.

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