Design Article
Optimize digital patterns for worst-case testing
Martin Rowe, Test & Measurement World
2/20/2012 11:57 AM EST
Complete validation of a high-speed serial link (28 Gbits/s) requires long patterns--some 2 billion bits. Long simulation run times and limitations in oscilloscope memory length make these tests time consuming and difficult. To combat the problem, engineers Masashi Shimanouchi, Mike Peng Li, and Daniel Chow of Altera studied how to optimize bit patterns and find the patterns that produce the worst-case amount of ISI (intersymbol interference) in a data stream. They reported the results in "Worst-Case Patterns for High-Speed Serial Link Simulation and Measurement" at DesignCon 2012. Masashi Shimanouchi presented the paper on Wednesday, February 1.
ISI occurs w hen energy from a bit interferes with adjacent bits because bits tend to stretch in time as they travel. Figure 1 shows how bits overlap and how their energy can accumulate in later bits.
Shimanouchi explained that you can design a short patterns of perhaps 10,000 bits to induce worst case ISI, but only if you know characteristics of the transmission channel, with settling time being a key parameter. That's because bit patterns can cause the DC level in a channel to change so they looked for patterns that cause the greatest changes in DC level, which is a combination of long and short He also noted that the worst-case pattern for a given link, which he called "Pathological worst case," might never occur in a real system. Thus, the engineers looked for patterns that, while less severe than the pathological worst case, are more likely to appear in a link.
In their study, the engineers looked at what causes worst-case eye height and worst-case eye width. These conditions occur when noise is injected in middle of eye, which affects height, or when noise is injected at transitions, which affects width. Thus, they set out to design a pattern that maximized both and then study the effects of those conditions on ISI. To to that, they used spectral analysis with a short-time Fourier Transform to find the channel loss versus frequency for worst save eye height and worst-case eye width. They measured the spectral response of the channel with and without pre-emphasis on the transmitted signals to see how pre-emphasis improves signal loss in the channel. By using these worst-case patterns, the engineers shortened test time. More work is needed to find even shorter worst-case patterns.
ISI occurs w hen energy from a bit interferes with adjacent bits because bits tend to stretch in time as they travel. Figure 1 shows how bits overlap and how their energy can accumulate in later bits.
Figure 1. Energy from bits can interfere with nearby bits, called intersymbol interference.
Shimanouchi explained that you can design a short patterns of perhaps 10,000 bits to induce worst case ISI, but only if you know characteristics of the transmission channel, with settling time being a key parameter. That's because bit patterns can cause the DC level in a channel to change so they looked for patterns that cause the greatest changes in DC level, which is a combination of long and short He also noted that the worst-case pattern for a given link, which he called "Pathological worst case," might never occur in a real system. Thus, the engineers looked for patterns that, while less severe than the pathological worst case, are more likely to appear in a link.
In their study, the engineers looked at what causes worst-case eye height and worst-case eye width. These conditions occur when noise is injected in middle of eye, which affects height, or when noise is injected at transitions, which affects width. Thus, they set out to design a pattern that maximized both and then study the effects of those conditions on ISI. To to that, they used spectral analysis with a short-time Fourier Transform to find the channel loss versus frequency for worst save eye height and worst-case eye width. They measured the spectral response of the channel with and without pre-emphasis on the transmitted signals to see how pre-emphasis improves signal loss in the channel. By using these worst-case patterns, the engineers shortened test time. More work is needed to find even shorter worst-case patterns.
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