As a starting point in design, traces should be properly isolated by spacing them at least three dielectric thicknesses from one another. As simulation and real-time network tests take place, the eye diagrams for signals should be monitored in real-time using test equipment intended for multi-gigabit speeds.
Planar discontinuities are likely to be encountered. The best defenses are proper signal termination and a board layout that is as straightforward and unencumbered as possible. Discontinuities can propagate through a design, however, when multilayer boards are used with multiple vias, via stubs and surface-mount components. The higher the number of devices with fast transmission edge rates, particularly surface-mount devices, the greater the discontinuity problem can become.
The device-specific edge rate challenge can have a direct impact on global board layout. Fast output edges and rise times on one device can eliminate or lessen the need for output equalization. Designs without output equalization are characterized by less crosstalk and lower power dissipation. The system designer must therefore choose specific devices carefully, mindful of the potential impact of those decisions on the layout of the entire board.
Equalization steps are particularly relevant in both transmitters and receivers. For the transmit side, output equalization can be performed in the digital domain using clocked drivers, or in the analog or time domain using single-decay and dual-decay preemphasis options.
On the receive side, designers may shy away from multistage analog and digital (nonlinear) equalization at first because it is more complex. Very high-speed designs, however, not only require high-frequency loss compensation but also must combat the effects of crosstalk and reflections. If the equalization characteristics of transmitters and receivers are carefully planned, interface boards may use twinaxial copper cables instead of fiber.
Figure 2. As multiple line cards populate a backplane, the need for equalization becomes obvious.
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Figure 3. Signal reflections can be responsible for as much as 10 percent of total crosstalk amplitude.
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In both transmit and receive channels, designers can take advantage of embedded electronic dispersion compensation (EDC), in which the decision feedback methods developed for long-haul fiber can be used in systems intended for the enterprise or metro-access network. Doing so might allow the replacement of single-mode fiber with multimode fiber. Once designers choose to use embedded EDC (either in high-integration transceivers or in discrete devices), however, care must be taken to use efficient algorithms and avoid degrading the signal of pristine channels. As backplane designers switch over from quad channels of 3 or 6 Gbits/s to a single, 10-Gbit serial channel in the 10GBase-KR standard, and as line-card interface developers turn to emerging transceiver modules such as SFP+ (small-form-factor pluggable) and CFP, the use of advanced equalizer chips in many cases is all but required.
Designers should recognize that waveform analysis becomes a much harder task once the use of transmit and receive equalization becomes commonplace. The clean and open eye diagrams encountered in 100-Mbit/s and 1-Gbit/s designs can become virtually indistinguishable from noise. Many semiconductor vendors are turning to embedded probe and test point technologies for high-speed line cards, and the most advanced designs offer full embedded waveform analysis accessible from the chip level. The most sensible location to embed such technology is in the clock and data recovery (CDR) device, after the equalizer and before the digital data-slicing function.
Broader use of embedded analysis carries fringe benefits beyond the real-time monitoring of eye diagrams in bench tests. A broad turn to CDR devices with embedded test allows for remote and continuous monitoring of network nodes for functions such as automatic protection switching—in essence, placing an oscilloscope everywhere within the system. If we assume that embedded probing and monitoring become commonplace, and that system-level designers can adopt a discipline to visualize system-level and device-level signal integrity simultaneously, then the methods used to support multiple channels of 10-Gbit support in a single design will help designers move to multiple 25-Gbit channels (used in the CFP2 version of 100-Gbit Ethernet). But it is important to remember that the old methods of designing traces for a circuit board, for using single-stage linear equalization and for observing waveforms without embedded probes will scarcely suffice as channel speeds exceed 3 Gbits/s and move to 10 and 28 Gbits/s.
Signal integrity at 10 Gbits/s and beyond is a brave new world, but it doesn’t have to be a scary one.
About the author
Kinana Hussain is the product marketing manager for Vitesse’s connectivity product portfolio. He graduated magna cum laude with a BSEE from California State University, Northridge, and holds an MBA from the University of California, Los Angeles’ Anderson School of Management. Hussain holds one patent and has a second one pending.