Ensuring synchronous sampling of multiple high-frequency signal channels

A burgeoning number of high-speed digitizer applications (100 MSa/s and greater, such as phased array radar test and flash radiographic facilities) require simultaneous measurement of high-frequency signals across multiple channels. Because current high-speed digitizers and oscilloscopes are limited to eight channels at the most, those applications having more channels and requiring precise time correlation between channels or accurate phasing of continuous signals demand synchronizing the sampling clocks of multiple instruments.

Synchronous sampling can be achieved by using proprietary trigger and clock distribution  busses included in high-speed digitizers (ASB bus [1] being one example)  However, these busses can only be used with a limited number of devices, and usually do not enable large scale multi-channel measurement.

By distributing a common, high-stability 10-MHz clock reference to all digitizers, it is possible to easily achieve synchronous sampling across a greater number of acquisition channels. One important challenge remains: measuring sub-nanosecond time delays between the synchronous samples of different channels. This article presents a method for measuring sampling-clock delay using the acquired signal as a time reference.

Achieving synchronous sampling
Accurate time correlation requires synchronous sampling across multiple digitizers and multiple channels [2].This can be required when analyzing multi-channel single-shot events, for example, or when digital signal processing (DSP) operations combine samples from different signal channels before processing the data.

Although it is possible to achieve multi-channel synchronous sampling by distributing a common sampling clock to the various modules, this presents a major technical challenge at high frequencies. As one example, the backplane busses and connectors may not well be suited to high-frequency signals, and above about 100 MHz, clock pulse edges deteriorate significantly and induce jitter. Using coaxial cables and proper connectors requires costly high-frequency fan-outs.

Another way to achieve synchronous sampling is to lock each digitizer’s sample-clock generator to a common high-stability 10-MHz reference signal. By feeding the frequency reference to every module, the “sampling instants” on all channels will be synchronous (e.g., the sampling-clock delay between any two channels will be constant).

The sampling-clock delay includes all delays due to factors such as delay lines, signal path lengths, and cable lengths (for the 10-MHz frequency reference). To verify that the criteria for synchronous sampling are satisfied, this delay must be shown to be constant. The sampling instants Ti are equally spaced (within the clock jitter) and have an interval equal to the inverse of the sampling frequency. With constant sampling-clock delay, the waveform data can be resampled using interpolation to yield a waveform with samples taken at exactly the same instants as the chosen reference channel. In cases that require data from several channels to be combined in DSP operations, it may be necessary to measure the sampling-clock delay to allow data resampling.