Linearity testing for G.hn PLC line drivers (Part 2)

Home wideband power line Communications (PLC) networks are pushing the transmit frequencies through 50 MHz now, headed towards 100 MHz carriers. The line driver must deliver the desired signal onto a difficult load, while not introducing a non-linear load during its shutdown for this TDMA system.

These systems act like a party line on the in-home power lines, where a single transmitter is enabled while all other PLC ports show a disabled line driver in parallel with the receivers. So those disabled ports must be able to receive the signal without introducing excessive nonlinearity into the broadband load.

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This second part of a two-part series reviews test methodology and data on a 3rd generation wideband differential driver.

Part 1 described the signal source generation and measurements for a 50MHz PLC signal at full line power of 15dBm with 14.6dB PAR using the ISL15100 driving a 34.6Ω load where <-50dBc MTPR was measured up through the power cutback frequency of 30Mhz. Part 1 is at this URL.

Part 2, below, adds a 2nd driver to the load network showing a measurement setup for introducing this active load while tapping off the transmit signal for MTPR degradation measurement. Lab measurements with disabled drivers added to the measurement load show negligible change to transmit MTPR performance relative to earlier devices.

PLC system requirements for disabled drivers
In a minimal 2-transceiver system, each port must both send and receive signal as shown in figure 10 for this TDMA system.


Click on image to enlarge.

Consider the line driver to the left as a transmitter while the Rxb is receiving with Txb disabled. Full power using a +12V supply produced approximately 6.2Vp differential at the output side of the Rbm resistors for a nominal line impedance of 100Ω.

That will get stepped up by the transformer (1:1.7 assumed here) and then down again going to Rxb port. For worst case, develop the maximum 7.9V peak swing at the receiver resistors and measure the MTPR with the disabled driver either inserted into the test board or removed. This 7.9Vp should be slightly higher than physical systems but will be used as worst case. There will be some degradation in the MTPR performance for these highest swings into the disabled port but far less than earlier line drivers with the simple power shutdown disable feature. Newer devices like the ISL15100 include active circuitry during the shutdown mode to bootstrap out the output transistor network when disabled from whatever signal is being sensed at the output pins.

Evaluation board circuit for differential PLC line drivers
For lab characterization, the circuit of figure 11 is used where instead of a single +12V supply, split +/-6V supplies are used. This eliminates some of the DC level shifting inconvenience in a lab environment.


Click on image to enlarge.

There are numerous optional elements in the EVAL circuit that are there, but not populated, for this test. The test input signal arrives at INA&INB from the post amplifier of fig. 3. That 2MHz minimum carrier is AC coupled to the 49.9Ω terminations (RSA & RSB). Probe points at this input signal are added through J1 and J2. The Cg capacitor is a short for this test but can be inserted to limit any DC output current that might be generated due to an output differential offset voltage. The RFA, RFB and RCG resistors are set to get the gain of 25dB intended in this example. The CLA and CLB capacitors are not populated but intended to provide a means of testing stability with small parasitic layout capacitance in the design. It is always best to reduce if possible any source of parasitic C directly on the output pins of these high speed drivers.

The target differential output swing is measured at J4 – J3 and should be ≈7.9Vp for full line power using the intended 1:1.7 turns ratio to a 100Ω line. Figure 12 shows a typical time waveform probing at J4&J3. Recall the differential swing is double this Vp number as the two outputs reverse polarity.


Click on image to enlarge.


The 7.9Vp swing at the output pins is reduced to 6.5Vp at the T2 test point of Figure 11 by the resistive loss through the Rb resistors (3.9Ω each) to an assumed 34.9Ω load. Since this is a general purpose test circuit, the resistor elements in the pi structure can be modified to implement different input and source impedances assuming different measurement impedances after this board. Here, R1->R4 are set to show a differential load of 34.9Ω and present 25Ω source on each output leg. This then feeds a transformer board to get back to single ended in a 50Ω measurement system. This is used for all of the amplifier frequency response and distortion measurements. Elements R2, R3, & R4 are intended to present a 400Ω differential input impedance converted to 50Ω differential output impedance where that 400Ω input assumes a matched 50Ω load going off board (ref. 6). This allows 50Ω cabling to be inserted without reflection or VSWR issues modifying the measurements. This network does insert ≈-24.6dB insertion loss. Since the full scale input for the DAQ board (ref. 3) is 200mVpp, this test will still require a bit more added attenuation as shown in the test block diagram of figure 1.
 
Adding a disabled line driver into the load circuit

One approach to inserting a disabled line driver would be to emulate the actual 100Ω line impedance at the outputs of the 2 Rba and Rbb resistors of fig. 11 using another 2- transformer board with the intended disabled line driver between those two transformers. Figure 11 could have been modified to a custom board with a disabled line driver attached at T2, but this approach allows separate “DUT” loads to be tested without customizing the general characterization board of fig. 11.