Design Article
Accelerate time-to-market by saving ESD test time
Charvaka Duvvury and Joel Dobson, Texas Instruments
11/21/2012 8:00 AM EST
Electrostatic discharge (ESD) qualification processes have become complex and expensive with the increased cost of ESD test time due to the industry trend toward higher package pin counts for ICs. This increasing demand for routine ESD testing of every pin can be mitigated by testing only a fraction of the pins while preserving the same data quality from the test results.
To reduce test times, increase qualification speed and preserve accuracy, an intelligent sampling method can be applied to groups of pins that share the same applications. Not only does the proposed method help accelerate time to market, it builds a bridge amongst the commonly disconnected disciplines of statistics, design and test engineering.
Test time complexities
As a part of IC product qualification, test times and test resources have become an increasing burden during evaluation for ESD. Therefore, a new approach would not only be unprecedented, but also it could lead to a venue of new ways for obtaining critical information in an expedient manner.
For semiconductor IC designs, it is now common practice to implement identical IO pins (clones) that have the same function with the same exact ESD protection cell. The clones share the same buffers and have the same macro name to identify them. In some cases, their population can be up to 70 percent of the total pin count for the device. The benefit for test time saving is significant for these cases, especially when the IC package pin counts exceed 3000.
Statistical methods for ESD
Statisticians and industrial engineers have long known how to estimate the sigma of a population using the range from a sample, assuming the data comes from a normal distribution [1]. The expected value of the range is proportional to the sigma (Fig. 1).
Click on image to enlarge.
Figure 1: The expected value, E, used in statistics as a function of the
range, R, in terms of factor d2. The d2 plot represents the number of
Sigmas that fit within the distribution. For example, there are 4.082
Sigmas with 30 readings.
The proportionality constant increases as the size of the sample increases. Using the sample range as a proxy for the population sigma is convenient and easy, forming a desirable heuristic, and is commonly used in semiconductor statistical process control analyses.
Testing the sample range is ideal if failure levels are assumed to be normally distributed. The central limit theorem says that a superposition of independent random variables tends toward normality, regardless of the distribution of the random variables contributing to the sum. The many physical variations manifested in an ESD reading may average out, leading to normally distributed ESD readings. In a recent study, the ESD readings from the identically designed pins appear to come from a normal distribution [2]. Figure 2 shows a typical distribution.
Click on image to enlarge.
Figure 2: Typical data taken on cloned IO pins with step voltages
showing a normal distribution range R from V1 (max voltage where no pins
fail) to V2 (min voltage where all pins fail). VM represents the level
where 50% or more pins result in failure. LSL denotes the chosen spec
level that all pins must pass for the product to be qualified.
For a possible application of sampling, one has to accept that all of the untested pins (i.e. untested clones) would give similarly distributed readings as the selected pins. But for the method to work, such distributions have to be established relative to the desired lower specification limit (LSL). The process for ready application of sampling becomes more practical when the LSL and sampled readings are farther apart (Fig. 3).
Click on image to enlarge.
Figure 3: The distance from LSL to the mean VM represents the number of
Sigmas for the distribution. The farther VM is from LSL, the lower is
the required sampling number to insure that all the unmeasured cloned
IOs are still above the LSL.
Next: A practical method
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dick_freebird
11/26/2012 11:39 AM EST
There are some assumptions (or ignored effects)
here that bear checking. Particularly, that the
I*R drops in the bussing are insignificant (not
true on large "low power" chips); that the same
ESD clamp cell is guaranteed to be hooked up the
same everywhere it's used (you can get very
different results by feeding a stripe from
opposite ends, vs same end in/out) and of course
the sensitivity of whatever's inboard of the cell
is unknown a priori.
In custom analog land, you might as well forget
all this. Even for a structured ASIC or standard
cell library, for this approach to work requires
additional design style constraint and/or per-
pin characterization to prove the validity of ignoring "should be same"
pins.
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Joy at TI
4/25/2013 2:26 PM EDT
We are sorry for the delay in our response as this was brought to our attention only recently, but we appreciate your comments. Here are our specific replies to your concerns.
"There are some assumptions (or ignored effects) here that bear checking. Particularly, that the I*R drops in the bussing are insignificant.."
This method was developed primarily for high pin count digital products. These products often use a common general purpose I/O cell that is cloned to form I/O banks. Many of these designs have distributed power clamps in each placement of the general purpose I/O cells and they are designed to have the same effective bus resistance to the supply clamp. Effectively these cloned I/O cells are identical. Once established through design checks (mandatory) that the pins are clones in every sense of the definition, the method uses random selection of these clones (a minimum of 30) to study their variations. The distribution of the data is then used to predict the unmeasured clones. All or any variations of bus resistance and inherent process variations are automatically covered under this approach. There are enough built-in checks for the method with very conservative criteria such that a 99% confidence level is guaranteed for application of the method.
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Joy at TI
4/25/2013 2:28 PM EDT
To respond to this other comment ("In custom analog land, you might as well forget all this.."):
This method may not be applicable to custom analog designs. These products typically have custom I/O cells such that the method would not work anyway (must stress a minimum of 30 identical clones). The pre-work required to validate the method, limits the practical application to only high pin count products. Thus the method was designed with a narrow applicability. However, there are already several large processor designs with several hundreds of cloned IO pins in production that can greatly benefit from this sampling method.
After much more scrutiny during the last 3 months a final optional test standard to be used for products with numerous cloned IO pins has been developed. This is expected to become part of the JEDEC/ESDA Joint HBM Standard in the near future.
Thank you again for your response and feedback!
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