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Design Article

# Accelerate time-to-market by saving ESD test time

## 11/21/2012 8:00 AM EST

A practical method

Ideally, if the sampled ESD readings are bounded from above and below, with a gap between the smallest readings and the LSL, then one can make inferences regarding the pins that were not sampled.  Statistical confidence statements can be made with regard to the proportion that is likely to fall below the LSL among the pins that were not sampled.

An applied sampling method has to be simple and practical. First, the failure distribution of the clone pins should be Gaussian in nature with a reasonably tight range (R) as determined by the distance between the maximum voltage where all pins still pass (V1), and minimum voltage where all pins fail (V2).  With this value of R, the Sigma (σ) for the distribution can be estimated.

But how many data readings are necessary? From known statistics for normal distribution, the expected value of the range is a multiple of σ with the multiple as a function of the count of readings.  It turns out that 30 is a practical count for which the range R would be within about four sigmas (Fig. 1).  For distributions that are Gaussian in nature, the Min voltage and the mid-range voltage where half of the pins fail (VM) can be used with equal accuracy (Fig. 2). Find the V1 and VM values by simply selecting 30 random clones and testing until half of them fail.  The number of sigmas that can fit between LSL and VM determines the cumulative distribution function (CDF) at the LSL (Fig. 3). The CDF at the LSL represents the proportion out of the specification for each sampled pin.

The final step is to extend the probability to insure that all the unmeasured pins still are above LSL with a confidence level of 99 percent. In summary, this approach enables information collected on just 30 identical pins to be used to determine the required sampling number with a confidence level of 99 percent such that all cloned pins are validly represented by our ESD test sample.

ESD sampling

To use the proposed method, failure data has to be collected on the identical clones sample with stepped voltages until half of them fail.  For the cloned IO pins, their ESD failure distributions will follow a common behavior since the same protection device governs their failure levels.  Some variations are expected due to physical differences in the IC layout and the failure thresholds derived by thermal limits due to process effects. Sampling is applied once conditions are met.

To illustrate, suppose there are N clones and 30 are selected to measure the maximum voltage point where none of them fail (V1) and the voltage point where half of the 30 pins fail (VM).  The range is estimated as twice the difference between VM and V1.  The range and the distance from LSL to VM can be applied as described above to find the required sampling, n, for a confidence level of (1-α). Application of this method has shown that if V1 is 2X of LSL, only about 10% of the clones need to be used for ESD testing (Fig.4).

Click on image to enlarge.

Figure 4: Predicted sampling curves for 300 cloned IOs. The required sampling as a function of distance from LSL to V1 for distributions with different ranges. The method becomes more viable and practical with tighter distribution (the curves shown on the left).

In general, the farther away V1 is from LSL and the tighter the range, the better the benefit from sampling (Fig. 4).  Significant test time savings can be achieved for IC products comprised of hundreds of clones without compromising ESD test accuracy.

Test time savings

The reason to sample is to save time and money. But even more important is the savings in qualification time and improving time to market. For example, it is often the case that when large numbers of identical pins are tested for ESD, the spurious variations that can result in the data cannot be replicated a second time or a third time. The probability for this to occur increases as the pin count increases, so the first step in intelligent testing is to remove these uncertainties and focus on the real issues.

Interdisciplinary efforts and the future

This new ESD sampling, presented at the 2012 ESD Symposium, was developed by a joint committee of ESD Association Standards representing several major IC suppliers and included inputs from people with engineering and mathematical backgrounds. The collaboration among various disciplines is an example of the path necessary to take in order to succeed in the increasingly competitive semiconductor industry landscape.  There is a need for interdisciplinary scientific development similar to the paradigm existing among departments at most major universities.  The Joint Electron Devices Engineering Council and the ESD Association Standards have preliminarily accepted the intelligent sampling method, pending an official documentation for ballot approval.

References
[1] Grant and Leavenworth, Statistical Quality Control, McGraw Hill Series.
[2]. C. Duvvury, J. Dobson, R. Gauthier, E. Grund, B. Carn, W. Stadler, J. Miller, T. Welsher, R. Gaertner, S. Ward, M. Chaine, A. Righter, “Sampling Pin Approaches for ESD Applications,” Presented at the EOS/ESD Symposium, September 12-14, 2012, Tucson, AZ.

Charvaka Duvvury is a Texas Instruments Fellow and an IEEE Fellow, working in the Advanced CMOS Technology Development. He is also a member of the Board of Directors for the ESD Association since 1997. His current work is on development and company wide support on ESD for the nanometer submicron CMOS technologies. Charvaka is co-founder and co-chair of the Industry Council on ESD Target Levels whose mission is to establish safe and realistic component ESD target levels while meeting the silicon technology challenges.

Joel Dobson has been working at Texas Instruments for 21 years where he is a Distinguished Member of the Technical Staff.  He is currently working as a corporate statistics expert with specializations semiconductor reliability, quality control and statistical modeling. Dobson is an Accredited Professional Statistician of the American Statistical Association and certified as a Quality Engineer, a Six Sigma Green Belt, and a Six Sigma Black Belt from the American Society of Quality.

dick_freebird

11/26/2012 11:39 AM EST

There are some assumptions (or ignored effects)
here that bear checking. Particularly, that the
I*R drops in the bussing are insignificant (not
true on large "low power" chips); that the same
ESD clamp cell is guaranteed to be hooked up the
same everywhere it's used (you can get very
different results by feeding a stripe from
opposite ends, vs same end in/out) and of course
the sensitivity of whatever's inboard of the cell
is unknown a priori.

In custom analog land, you might as well forget
all this. Even for a structured ASIC or standard
cell library, for this approach to work requires
additional design style constraint and/or per-
pin characterization to prove the validity of ignoring "should be same"
pins.

Joy at TI

4/25/2013 2:26 PM EDT

We are sorry for the delay in our response as this was brought to our attention only recently, but we appreciate your comments. Here are our specific replies to your concerns.
"There are some assumptions (or ignored effects) here that bear checking. Particularly, that the I*R drops in the bussing are insignificant.."
This method was developed primarily for high pin count digital products. These products often use a common general purpose I/O cell that is cloned to form I/O banks. Many of these designs have distributed power clamps in each placement of the general purpose I/O cells and they are designed to have the same effective bus resistance to the supply clamp. Effectively these cloned I/O cells are identical. Once established through design checks (mandatory) that the pins are clones in every sense of the definition, the method uses random selection of these clones (a minimum of 30) to study their variations. The distribution of the data is then used to predict the unmeasured clones. All or any variations of bus resistance and inherent process variations are automatically covered under this approach. There are enough built-in checks for the method with very conservative criteria such that a 99% confidence level is guaranteed for application of the method.

Joy at TI

4/25/2013 2:28 PM EDT

To respond to this other comment ("In custom analog land, you might as well forget all this.."):
This method may not be applicable to custom analog designs. These products typically have custom I/O cells such that the method would not work anyway (must stress a minimum of 30 identical clones). The pre-work required to validate the method, limits the practical application to only high pin count products. Thus the method was designed with a narrow applicability. However, there are already several large processor designs with several hundreds of cloned IO pins in production that can greatly benefit from this sampling method.

After much more scrutiny during the last 3 months a final optional test standard to be used for products with numerous cloned IO pins has been developed. This is expected to become part of the JEDEC/ESDA Joint HBM Standard in the near future.

Thank you again for your response and feedback!