The future is high-level synthesis (HLS). As a developer of HLS software, Forte’s vision for this methodology is far reaching and all inclusive, and one we’ve considered for some time. We share a common belief with other HLS developers that it will replace the register transfer level (RTL) as the predominant front-end design methodology and will be used to do everything logic synthesis can do today.
The semiconductor industry is not there yet, and getting to that point will clearly take time, both in terms of extending the capabilities of the technology and driving adoption by the design community, but the trend is clear. The transition from gate-level design to RTL set a clear precedent. The industry saw the adoption of new tools, development of designs and intellectual property (IP) and, eventually, the bulk of designs and IP exist in the form of RTL code.
A number of key drivers and requirements enable such a methodology transition, beginning with productivity. Productivity is increased through the delivery of a more abstract design language. Back in the day, when hardware designers transitioned from assembly code to high-level languages for software development, they saw a huge increase in productivity, delivered by abstraction. Coders could add significantly more functionality with less lines of code; debugging was easier; maintenance was easier; code was more understandable; and reuse was increased.
These same designers experienced the same kind of change when hardware design transitioned from gate level to RTL. And, it will happen again as design teams transition to C++ from Verilog and VHDL.
However, abstraction on its own is not enough for hardware design. Designing a chip with complex behavior is a huge undertaking with many engineers assigned to various aspects of the project. A hardware design language must support the partitioning of the design into smaller chunks to provide manageable pieces for tools and scalability, to divide work among separate engineers or teams and chip functionality into sensibly reusable pieces. Key additions to a language to support such partitioning are modules, hierarchy and interfaces, something found in C++.
It is also critical to consider not only the final state of HLS deployment, but how design teams transition to that state. This will be a gradual transition, and during that time, blocks designed using HLS must coexist with blocks designed with RTL languages. They must interface cleanly and consistently, simulate together and merge well during implementation.
And, that’s the task set in front of developers of HLS technology: to deliver a methodology that increases productivity through abstraction and also deals with the practical issues of partitioning and integration with existing design blocks. These issues need to be carefully considered and solved to get all the way to the end.
That’s why many of us have chosen SystemC as the design language for HLS. Plain old C++ may seem logical when first considering a move to HLS, and it can be a useful utility for block-level experimentation. But when design teams look more closely at the problem, they will recognize that they will never be able to replace their entire RTL design flow without the extensions that SystemC delivers.
The transition from RTL to HLS as the predominant front-end methodology is under way. As the design community will soon discover, SystemC will be a ready enabler for this move.
About the author:
is president and CEO of Forte Design Systems Inc. (San Jose, Calif.)
Dart joined Forte Design Systems Inc. in 1997 and has over 20 years of software design experience, with 14 of those years in EDA. Prior to joining Forte, he was the CTO of Speed Electronics S.A., a company specializing in front-end design tools for logic synthesis flows. Prior to Speed, Dart held a number of software management and development positions in the fields of telecommunications and operating systems development. Dart graduated from the University of N.S.W. in Sydney, Australia.